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1.发明申请公开(公告)号：US20220286329A1
公开(公告)日：2022-09-08
申请号：US17711328
申请日：2022-04-01
Applicant: Rambus Inc.
Inventor： Reza Navid
Abstract: A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.
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公开(公告)号：US20160072440A1
公开(公告)日：2016-03-10
申请号：US14858965
申请日：2015-09-18
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Reza Navid
Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
Abstract translation: 锁相环电路包括具有多个耦合振荡器的多相振荡器。 校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。 校准模块然后校准各种振荡器以补偿检测到的失配。 一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。
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公开(公告)号：US08964879B2
公开(公告)日：2015-02-24
申请号：US13937549
申请日：2013-07-09
Applicant: Rambus Inc.
Inventor： Reza Navid , Amir Amirkhany , Dinesh D. Patil , Brian S. Leibowitz
CPC classification number: H04L1/0083 , H04L1/0001 , H04L1/0002 , H04L1/0007
Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.
Abstract translation: 数据编码方案执行基于电平和/或基于转换的编码，以避免在通过并行通信链路将多位数据从一个电路传输到另一电路时产生最差情况串扰的信令条件。 编码方案不允许某些模式存在于信号电平，信号转换或信号电平和信号转换的组合中，信号电平和信号转换发生在对应于并行通信链路的某些物理相邻电线的多位数据的子集中 。
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公开(公告)号：US20170324594A1
公开(公告)日：2017-11-09
申请号：US15491237
申请日：2017-04-19
Applicant: Rambus Inc.
Inventor： Reza Navid
CPC classification number: H04L25/4917 , H04L25/03343 , H04L2025/03363
Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.
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公开(公告)号：US09722539B2
公开(公告)日：2017-08-01
申请号：US14858965
申请日：2015-09-18
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Reza Navid
Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
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Patent Agency Ranking
公开(公告)号：US20160190986A1
公开(公告)日：2016-06-30
申请号：US14960065
申请日：2015-12-04
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US20160149730A1
公开(公告)日：2016-05-26
申请号：US14952016
申请日：2015-11-25
Applicant: Rambus Inc.
Inventor： Reza Navid
IPC: H04L25/03
CPC classification number: H04L25/4917 , H04L25/03343 , H04L2025/03363
Abstract: A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.
Abstract translation: 发射电路可以被配置为输出两级脉冲幅度调制（PAM-2）或四级脉冲幅度调制（PAM-4）。 在PAM-2模式中，预抽头前馈均衡（FFE）和后抽头FFE可以分别通过预抽头和后抽头应用于PAM-2信号。 在PAM-4模式中，至少一个后抽头被重新利用以与主抽头一起产生主PAM-4信号电平。 至少有一个PAM-2 FFE抽头被重新利用以在PAM-4模式下应用FFE。
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公开(公告)号：US08933729B1
公开(公告)日：2015-01-13
申请号：US13834970
申请日：2013-03-15
Applicant: Rambus Inc.
Inventor： Xudong Shi , Reza Navid , Jason Chia-Jen Wei , Huy M. Nguyen , Kambiz Kaviani
CPC classification number: H03K5/00 , H03F3/195 , H03F3/45179 , H03F3/45654 , H03F3/68 , H03F2203/45418 , H03F2203/45424 , H03F2203/45498 , H03F2203/45702 , H04L25/0276
Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.
Abstract translation: 差分接收器“堆叠”，并独立校准到不同的共模电压。 不同的共模电压可以对应于堆叠的发送电路的共模电压。 多个采样器堆叠连接到相同的通道。 每个采样器电路堆的时钟被定时（定时），使得给定堆栈中的采样器不能同时解析。 在不同的堆叠中并且接收不同共模电压的采样器同时解析。
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公开(公告)号：US20140380082A1
公开(公告)日：2014-12-25
申请号：US14482782
申请日：2014-09-10
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
Abstract translation: 描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。 本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位 进入国际劳工组织。
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公开(公告)号：US20140015615A1
公开(公告)日：2014-01-16
申请号：US13925330
申请日：2013-06-24
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Reza Navid
IPC: H03L7/06
Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
Abstract translation: 锁相环电路包括具有多个耦合振荡器的多相振荡器。 校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。 校准模块然后校准各种振荡器以补偿检测到的失配。 一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。
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