公开(公告)号：US11853115B1

公开(公告)日：2023-12-26

申请号：US17953458

申请日：2022-09-27

Applicant: Astera Labs, Inc.

Inventor： Jitendra Mohan ,  Subbarao Arumilli ,  Charan Enugala ,  Chi Feng ,  Ken (Keqin) Han ,  Pulkit Khandelwal ,  Vikas Khandelwal ,  Casey Morrison ,  Enrique Musoll ,  Vivek Trivedi

IPC: G06F1/12 ,  G06F1/06 ,  H03K5/00

CPC classification number: G06F1/12 ,  G06F1/06 ,  H03K5/00 ,  H03K2005/00019

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

公开(公告)号：US11828776B2

公开(公告)日：2023-11-28

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G01R19/165 ,  G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07

CPC classification number: G01R19/16533 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/0772 ,  G06F21/755 ,  H01L23/576 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058 ,  H03K2005/00078

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US11784610B2

公开(公告)日：2023-10-10

申请号：US17190570

申请日：2021-03-03

Applicant: NXP USA, Inc.

Inventor： Anthony Lamy ,  Olivier Lembeye

IPC: H03F1/02 ,  H03F3/21 ,  H03K5/00

CPC classification number: H03F1/0288 ,  H03F3/21 ,  H03K5/00 ,  H03F2200/451 ,  H03K2005/00286

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.

公开(公告)号：US11764761B2

公开(公告)日：2023-09-19

申请号：US17669338

申请日：2022-02-10

Applicant: Fermi Research Alliance, LLC

Inventor： Jinyuan Wu

IPC: H03K3/03 ,  H03K3/012 ,  H03K19/20 ,  H03K5/00

CPC classification number: H03K3/0315 ,  H03K3/012 ,  H03K5/00 ,  H03K19/20 ,  H03K2005/00078

Abstract: A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

公开(公告)号：US20190222205A1

公开(公告)日：2019-07-18

申请号：US16248159

申请日：2019-01-15

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Sungku YEO ,  Gwanghyeon JEONG ,  Songcheol HONG ,  Jaeseok PARK ,  Seunghun WANG ,  Youngho RYU ,  Junhan LIM

IPC: H03K5/00 ,  H03H11/32 ,  H03M1/66 ,  H03K17/687

CPC classification number: H03K5/00 ,  H02J50/10 ,  H03H11/32 ,  H03K17/687 ,  H03K2005/00286 ,  H03M1/66

Abstract: A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

公开(公告)号：US09847839B2

公开(公告)日：2017-12-19

申请号：US15061923

申请日：2016-03-04

Applicant: INPHI CORPORATION

Inventor： Karthik Gopalakrishnan ,  Jamal Riani ,  Arun Tiruvur

IPC: H04B10/00 ,  H04B10/40 ,  H04L7/00 ,  H04L7/033 ,  H04B10/54

CPC classification number: H04B10/40 ,  H03K5/00 ,  H03K19/018521 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/23 ,  H03L2207/06 ,  H04B10/541 ,  H04L7/0037 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/0331 ,  H04L25/00

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

公开(公告)号：US20170338941A1

公开(公告)日：2017-11-23

申请号：US15159583

申请日：2016-05-19

Applicant: OmniVision Technologies, Inc.

Inventor： Li YANG ,  Wengen WANG ,  Charles Qingle WU

IPC: H04L7/033 ,  H04L5/00 ,  H04B1/69

CPC classification number: H04L7/0331 ,  G06F1/08 ,  H03K3/84 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/131 ,  H03K5/133 ,  H03K5/14 ,  H03L7/16 ,  H04B1/69 ,  H04B15/02 ,  H04L5/005

Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

公开(公告)号：US09692376B2

公开(公告)日：2017-06-27

申请号：US14214709

申请日：2014-03-15

Applicant: David Schie

Inventor： David Schie

IPC: H02J7/34 ,  H02J1/10 ,  H02J3/38 ,  H03F3/45 ,  H03K5/00

CPC classification number: H03F3/45475 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03K5/00 ,  Y10T307/549

Abstract: A switched capacitor circuit including two or more capacitors arranged in a switched capacitor circuit configuration with a comparator comparing a node whose potential varies with the charging of one or more of the switched capacitors. The switched capacitor circuit also has two or more current sources scaled relative to one another coupled to the capacitors and to the comparator, where the current from one current source charges at least two of the capacitors in series during the charge portion of the cycle, and the other current source charges at least one of but at least one fewer of the capacitor(s) during the charge portion of the cycle, and where the current sources are enabled at the beginning of the charge portion of the cycle, but where the comparator disables the current sources once the node reaches a reference potential.

公开(公告)号：US20160352220A1

公开(公告)日：2016-12-01

申请号：US15166847

申请日：2016-05-27

Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.

Inventor： Taesung KIM ,  Seunguk YANG ,  Youngbae PARK

IPC: H02M3/07

CPC classification number: H03K5/00 ,  G06G7/16 ,  H03K4/502 ,  H03K4/94

Abstract: Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time.

Abstract translation: 信号计算器的示例包括电压倍增器和时分器。 电压倍增器复制对应于第一电压的时间信息，并且在对应于复制的时间信息的第一时段期间，使用对应于第二电压的第二电流来产生第三电压。 时分器根据将第一电流产生的电压与第一时间相对应的电压与对应于第二时间的第二电压进行比较的结果产生输出。

公开(公告)号：US20160254903A1

公开(公告)日：2016-09-01

申请号：US15078939

申请日：2016-03-23

Applicant: UNIQUIFY, INC.

Inventor： Mahesh Gopalan

IPC: H04L7/033

CPC classification number: H04L7/0337 ,  G06F1/08 ,  G06F11/0763 ,  G06F11/0793 ,  H03K5/00 ,  H03K19/01806 ,  H04L1/205

Abstract: A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Abstract translation: 公开了一种用于在集成电路接口中实现自适应位调平功能的电路和方法。 在校准操作期间，从发送设备连续地发送预加载的数据位模式，并且由接收设备从外部总线连续读取。 可编程延迟线都相对于采样点在时间上推进和延迟每个单独的数据位，并且针对不同的采样数据位值记录相对于参考点的延迟计数，使得能够确定最佳采样数据的延迟 位在它的中点。 在数据位的推进和延迟期间，数据位信号的抖动可能导致确定中点的模糊性，并且公开了用于检测抖动和解决用于采样数据位的中点的解决方案，即使存在 抖动。