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公开(公告)号：US12045378B2
公开(公告)日：2024-07-23
申请号：US17657212
申请日：2022-03-30
发明人： Franck Albesa , Nicolas Anquet
CPC分类号： G06F21/79 , G06F21/602 , H04L9/0894 , H04L9/14
摘要： The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
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公开(公告)号：US12045377B2
公开(公告)日：2024-07-23
申请号：US17657020
申请日：2022-03-29
发明人： Franck Albesa , Nicolas Anquet
IPC分类号： G06F21/32 , G06F9/4401 , G06F21/72 , H04L9/08
CPC分类号： G06F21/72 , G06F9/4401 , H04L9/0861
摘要： The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
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公开(公告)号：US20240120638A1
公开(公告)日：2024-04-11
申请号：US18545106
申请日：2023-12-19
发明人： Deborah COGONI
摘要： An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
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公开(公告)号：US20240077522A1
公开(公告)日：2024-03-07
申请号：US18355977
申请日：2023-07-20
发明人： Christophe Lorin , Nathalie Dubois
IPC分类号： G01R19/165 , G01R15/04
CPC分类号： G01R19/16576 , G01R15/04
摘要： A voltage matching circuit receives a first voltage received by a connector, and outputs a second voltage. The second voltage is equal to the first voltage, if the first voltage is less than a threshold voltage. The second voltage is equal to the first voltage divided by a first factor, if the first voltage is greater than or equal to the threshold voltage.
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公开(公告)号：US11879909B2
公开(公告)日：2024-01-23
申请号：US17869301
申请日：2022-07-20
IPC分类号： G01R31/00 , G01R31/26 , G01R31/28 , G01R1/02 , G01R1/04 , G01R1/067 , G01R1/073 , G01R1/18 , G01R1/24 , G01R1/28
CPC分类号： G01R1/0416 , G01R31/2808 , G01R31/2889
摘要： A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.
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公开(公告)号：US11853241B2
公开(公告)日：2023-12-26
申请号：US18065475
申请日：2022-12-13
发明人： Jawad Benhammadi , Sylvain Meyer
IPC分类号： G06F13/24 , G06F13/16 , G06F21/85 , H03K19/20 , G06F1/3237
CPC分类号： G06F13/24 , G06F1/3237 , G06F13/1689 , G06F21/85 , H03K19/20
摘要： In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
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公开(公告)号：US20230384953A1
公开(公告)日：2023-11-30
申请号：US18318416
申请日：2023-05-16
发明人： Jawad Benhammadi
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0655 , G06F3/0679
摘要： In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.
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公开(公告)号：US11823750B2
公开(公告)日：2023-11-21
申请号：US17244450
申请日：2021-04-29
CPC分类号： G11C16/3454 , G11C16/105 , G11C16/26 , G11C16/30 , G11C17/00
摘要： A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.
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公开(公告)号：US20230336176A1
公开(公告)日：2023-10-19
申请号：US18296325
申请日：2023-04-05
IPC分类号： H03K19/0185 , H03K19/20
CPC分类号： H03K19/018521 , H03K19/20
摘要： A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.
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公开(公告)号：US20230327666A1
公开(公告)日：2023-10-12
申请号：US18191491
申请日：2023-03-28
IPC分类号： H03K17/687 , H03K17/22 , H03K17/10
CPC分类号： H03K17/6871 , H03K17/223 , H03K17/102
摘要： In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.
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