Abstract:
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
Abstract:
The present disclosure is directed to a modular and scalable front-end architecture for a massive MIMO communication device, such as a base station. The front-end architecture can allow for the number of antennas at the communication device to be increased or decreased in a simple and cost efficient manner. The front-end architecture can also allow for the number of data streams that can be transmitted and/or received by the communication device to be increased or decreased in a simple and cost efficient manner.
Abstract:
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
Abstract:
The present disclosure is directed to a modular and scalable front-end architecture for a massive MIMO communication device, such as a base station. The front-end architecture can allow for the number of antennas at the communication device to be increased or decreased in a simple and cost efficient manner. The front-end architecture can also allow for the number of data streams that can be transmitted and/or received by the communication device to be increased or decreased in a simple and cost efficient manner.
Abstract:
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
Abstract:
A transceiver is disclosed which includes a transmitter and a receiver. The transmitter provides an impairment measurement signal, which is substantially similar to a transmitted communication signal except for a possible difference in phase and/or a magnitude, to the receiver. An envelope detector within the receiver provides an envelope of the impairment measurement signal to the transmitter. The transmitter determines sets of one or more filtering coefficients using the envelope of the impairment measurement signal and adjusts phases or magnitudes and/or phases of a sequences of bits used to generate the transmitted communication signal in accordance with the sets of one or more filtering coefficients to compensate for the unwanted distortion and/or the unwanted interference present within the transmitted communication signal.
Abstract:
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.