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公开(公告)号：US11601091B1
公开(公告)日：2023-03-07
申请号：US17793180
申请日：2020-12-28
申请人： OSAKA UNIVERSITY
发明人： Teruo Kanki , Yasushi Hotta
摘要： A fluctuating oscillator includes: an adder that has an input terminal to which an input signal including a main signal and an uncorrelated signal that is uncorrelated with the main signal and is higher in frequency than the main signal is input, and adds a feedback signal to the input signal; a threshold discrimination unit that generates a pulse signal by comparing an addition signal added by the adder with a threshold; a transient response unit that generates an output signal by transiently responding the generated pulse signal; and a feedback loop that feeds back the output signal to the adder as the feedback signal.
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公开(公告)号：US20190356321A1
公开(公告)日：2019-11-21
申请号：US15981948
申请日：2018-05-17
发明人： Igal Kushnir , Hung-Ming Chien , Wei-Hong Chen , Theodoros Chalvatzis , Seunghwan Yoon , Chin-Ming Chien , Tirdad Sowlati , Moche Cohen , Kobi Sturkovich , Shaul Klein
摘要： A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
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公开(公告)号：US10305499B2
公开(公告)日：2019-05-28
申请号：US15349220
申请日：2016-11-11
摘要： A frequency synthesizer includes: an oscillating section that generates a first signal; a frequency ratio measuring section that measures a frequency ratio of the first signal and a second signal by using the first signal and the second signal; a comparing section that compares the frequency ratio, which is measured by the frequency measuring section, with a target value of a frequency ratio; and a filter that is disposed on a preceding stage of the comparing section. A frequency of the first signal of the oscillating section is adjusted on the basis of a comparison result of the comparing section.
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4.发明授权公开(公告)号：US10103761B2
公开(公告)日：2018-10-16
申请号：US15275779
申请日：2016-09-26
申请人： Intel Corporation
发明人： Igal Kushnir , Gil Horovitz , Sarit Zur
摘要： Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.
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公开(公告)号：US09531324B1
公开(公告)日：2016-12-27
申请号：US14788958
申请日：2015-07-01
摘要： A frequency synthesizing circuit comprising a first mixer configured to receive a first input signal at a first input thereof, a first filter configured to receive an output signal of the first mixer and remove undesired signal frequencies from the output signal of the first mixer, and a feedback loop. The feedback loop includes a second mixer having a first input connected to the output of the first filter and a second input for receiving a second input signal. The second mixer is configured to mix a signal received at the first input with the second input signal. The feedback loop further includes a third mixer having a first input connected to an output of the second mixer and a second input for receiving a third input signal. The third mixer is configured to mix a signal received at the first input with the third input signal.
摘要翻译： 一种频率合成电路，包括：第一混频器，被配置为在其第一输入处接收第一输入信号;第一滤波器，被配置为接收第一混频器的输出信号，并从第一混频器的输出信号中去除不需要的信号频率， 反馈回路。 反馈环路包括具有连接到第一滤波器的输出端的第一输入端和用于接收第二输入信号的第二输入端的第二混频器。 第二混频器被配置为将在第一输入处接收到的信号与第二输入信号进行混合。 反馈环路还包括具有连接到第二混频器的输出端的第一输入端和用于接收第三输入信号的第二输入端的第三混频器。 第三混频器被配置为将在第一输入处接收的信号与第三输入信号混合。
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公开(公告)号：US09501087B1
公开(公告)日：2016-11-22
申请号：US14742369
申请日：2015-06-17
申请人： RAYTHEON COMPANY
CPC分类号： G06F1/0321 , G06F1/022 , G06F1/0328
摘要： A frequency-agile frequency source. The frequency source includes an oscillator having an output and being configured to generate a signal at a first frequency at the output, a first direct digital synthesizer (DDS) having an output and a sampling clock input connected to the output of the oscillator, a filter amplifier block having an input directly connected to the output of the first DDS and an output, and a second DDS having a sampling clock input directly connected to the output of the filter amplifier block. The filter amplifier block is a substantially linear time-invariant element having a frequency response, the magnitude of the frequency response being at least 12 dB lower, at a second frequency within the first Nyquist zone of the first frequency, than at a third frequency above the first Nyquist zone of the first frequency.
摘要翻译： 频率敏捷频率源。 频率源包括具有输出并被配置为在输出处以第一频率产生信号的振荡器，具有连接到振荡器的输出的输出和采样时钟输入的第一直接数字合成器（DDS），滤波器 具有直接连接到第一DDS的输出的输入和输出的放大器块，以及具有直接连接到滤波器放大器块的输出的采样时钟输入的第二DDS。 滤波器放大器块是具有频率响应的基本上线性的时间不变元件，频率响应的幅度在第一频率的第一奈奎斯特区内的第二频率处比在第三频率以上的第三频率处低至少12dB 第一个奈奎斯特区的第一个频率。
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7.发明授权Acoustically-engineered multi-port piezoelectric-on-semiconductor resonators for accurate temperature sensing and reference signal generation 有权声学设计的多端口压电半导体谐振器，用于精确的温度检测和参考信号生成公开(公告)号：US09318998B1
公开(公告)日：2016-04-19
申请号：US14015707
申请日：2013-08-30
发明人： Roozbeh Tabrizian , Farrokh Ayazi
CPC分类号： H03B5/323 , H01L41/09 , H03B5/04 , H03B5/30 , H03B5/32 , H03B21/00 , H03B21/01 , H03H9/2405 , H03H2009/241 , H03L1/02 , H03L1/021 , H03L1/022 , H03L1/027 , H03L1/028 , H03L7/00
摘要： An integrated circuit device includes a multi-port piezoelectric-on-semiconductor microelectromechanical resonator, which is configured to support independent and concurrent piezoelectric transduction of multiple resonance modes. The resonator includes a semiconductor resonator body (e.g., Si body) suspended opposite an underlying recess in a substrate. Opposite ends of the semiconductor resonator body are anchored to the substrate. The resonator body may be formed so that a plan layout view of a portion of the semiconductor resonator body is dumbbell-shaped to thereby support acoustic energy trapping of multiple high-Q resonance modes.
摘要翻译： 集成电路器件包括多端口压电半导体微机电谐振器，其被配置为支持多个谐振模式的独立且并发的压电换能。 谐振器包括与衬底中的下面的凹部相对悬挂的半导体谐振器体（例如，Si体）。 半导体谐振器体的相对端锚定到基板。 可以形成谐振器体，使得半导体谐振器体的一部分的平面布局图是哑铃形的，从而支持多个高Q谐振模式的声能捕获。
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公开(公告)号：US09184699B2
公开(公告)日：2015-11-10
申请号：US13829975
申请日：2013-03-14
发明人： Jose Pedro Moreira
CPC分类号： H03B21/00 , H03C5/00 , H03M1/66 , H04B1/0475 , H04B1/0483
摘要： Implementations of a high gain range transmitter with variable-size mixers are described.
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9.发明授权Circuit and method for adaptive clock generation using dynamic-time-average-frequency 有权使用动态时间平均频率的自适应时钟生成的电路和方法公开(公告)号：US09118275B1
公开(公告)日：2015-08-25
申请号：US14088500
申请日：2013-11-25
申请人： Liming Xiu
发明人： Liming Xiu
摘要： An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides. A method of creating such adaptive clock generation circuit is also presented.
摘要翻译： 一种用于以动态方式合成时间平均频率的自适应时钟产生电路包括：（a）用于产生固定时间跨度的基本单元的定时电路，（b）从微电子系统接收输入的控制电路，其中控制电路和 时钟生成电路用于产生更新信号和频率控制字，（c）用于通过利用所述基本单元和频率控制字来产生多种类型的脉冲的直接周期合成器，用于创建时钟段 通过根据更新信号连接从所述多种类型中选择的串联电脉冲，用于通过串联连接所述段来创建整个时钟脉冲串。 所得到的时钟脉冲串的时间 - 频率与时钟发生电路所在的微电子系统的操作所需的选定频率相匹配。 还提出了一种创建这种自适应时钟发生电路的方法。
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10.发明授权Variable phase shifter, semiconductor integrated circuit and phase shifting method 有权可变移相器，半导体集成电路和相移方法公开(公告)号：US09106180B2
公开(公告)日：2015-08-11
申请号：US14029040
申请日：2013-09-17
申请人： FUJITSU LIMITED
发明人： Masaru Sato
摘要： A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer.
摘要翻译： 可变移相器。 可变移相器包括：响应于特定频率的输入信号从一对输出端口输出正交信号的传输线; 合成器，其包括连接到所述一对输出端口的第一端口的第一晶体管和连接到所述一对输出端口的第二端口的第二晶体管，并且在所述输入信号的输入端从所述一对输出端输出的信号 传输线的端口根据其相应的负载阻抗具有相位，并且采用第一和第二晶体管来放大和组合信号; 以及相位控制器，其通过控制合成器的第一和第二晶体管的放大操作来控制由合成器组合和输出的输出信号的相位。
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