公开(公告)号：US20180309455A1

公开(公告)日：2018-10-25

申请号：US16017421

申请日：2018-06-25

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Paul PENZES ,  Mark FULLERTON

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/097 ,  G06F1/32 ,  G06F12/14 ,  G06F21/44 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  H03K5/133 ,  H03K5/00 ,  G06F1/26

CPC classification number: H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.