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公开(公告)号：US20180067535A1
公开(公告)日：2018-03-08
申请号：US15258816
申请日：2016-09-07
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Thomas Burd , Adam Clark , Larry D. Hewitt , John Vincent Faricelli , John P. Petry
CPC classification number: G06F1/3209 , G01R31/2856 , G01R31/2874 , G06F1/3206 , G06F1/3234 , G06F11/008 , G06F11/3409
Abstract: A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.
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公开(公告)号：US10218273B2
公开(公告)日：2019-02-26
申请号：US15632765
申请日：2017-06-26
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Erhan Ergin , Dipanjan Sengupta , Elsie Lo , Stephen V. Kosonocky , Sree Rajesh Saha , Divya Guruja
IPC: H02M3/158
Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
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公开(公告)号：US11936382B2
公开(公告)日：2024-03-19
申请号：US16454596
申请日：2019-06-27
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03L1/02 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K3/03 , H03K5/15 , H03L5/00 , H03L7/085 , H03L7/099 , H03K5/1534
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997 , H03K5/1534
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号：US20180374853A1
公开(公告)日：2018-12-27
申请号：US15632765
申请日：2017-06-26
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Erhan Ergin , Dipanjan Sengupta , Elsie Lo , Stephen V. Kosonocky , Sree Rajesh Saha , Divya Guruja
Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
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公开(公告)号：US10425089B2
公开(公告)日：2019-09-24
申请号：US15850593
申请日：2017-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
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Patent Agency Ranking
公开(公告)号：US10382014B2
公开(公告)日：2019-08-13
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03K3/03 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K5/1534 , H03K5/15 , H03L5/00 , H03L7/099 , H03L1/02 , H03L7/085
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号：US20190199363A1
公开(公告)日：2019-06-27
申请号：US15850593
申请日：2017-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
CPC classification number: H03L7/0992 , G06F1/08 , H03B1/04 , H03K3/0307 , H03K3/0372 , H03K2005/00071
Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
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公开(公告)号：US10120430B2
公开(公告)日：2018-11-06
申请号：US15258816
申请日：2016-09-07
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Thomas Burd , Adam Clark , Larry D. Hewitt , John Vincent Faricelli , John P. Petry
Abstract: A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.
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公开(公告)号：US20180183413A1
公开(公告)日：2018-06-28
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03K5/1534 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号：US12111716B2
公开(公告)日：2024-10-08
申请号：US18304849
申请日：2023-04-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Mihir Shaileshbhai Doctor , Alexander J. Branover , Benjamin Tsien , Indrani Paul , Christopher T. Weaver , Thomas J. Gibney , Stephen V. Kosonocky , John P. Petry
IPC: G06F1/32 , G06F1/3234 , G06F1/3287 , G06F1/3296
CPC classification number: G06F1/3287 , G06F1/3265 , G06F1/3278 , G06F1/3296
Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.
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