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公开(公告)号：US12001265B2
公开(公告)日：2024-06-04
申请号：US17483694
申请日：2021-09-23
发明人： Benjamin Tsien , Alexander J. Branover , Christopher T. Weaver , Indrani Paul , Mihir Shaileshbhai Doctor , John P. Petry , Stephen V. Kosonocky , Thomas J. Gibney , Jose G. Cruz , Pravesh Gupta , Chintan S. Patel
IPC分类号： G06F1/00 , G06F1/3234 , G06F3/06 , G06F11/14
CPC分类号： G06F1/3275 , G06F1/3265 , G06F3/0625 , G06F3/0635 , G06F3/0673 , G06F11/1469 , G06F2201/84
摘要： Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.
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公开(公告)号：US20230315188A1
公开(公告)日：2023-10-05
申请号：US17710521
申请日：2022-03-31
发明人： Alexander J. Branover , Thomas J. Gibney , Mihir Shaileshbhai Doctor , Indrani Paul , Benjamin Tsien , Stephen V. Kosonocky , John P. Petry , Christopher T. Weaver
IPC分类号： G06F1/3234
CPC分类号： G06F1/3234
摘要： Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.
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公开(公告)号：US20230095622A1
公开(公告)日：2023-03-30
申请号：US17485194
申请日：2021-09-24
发明人： Alexander J. Branover , Indrani Paul , Benjamin Tsien , Christopher T. Weaver , John P. Petry , Mihir Shaileshbhai Doctor , Thomas J. Gibney
摘要： A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.
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公开(公告)号：US20230031295A1
公开(公告)日：2023-02-02
申请号：US17390475
申请日：2021-07-30
发明人： Thomas J. Gibney , Alexander J. Branover , Mihir Shaileshbhai Doctor , Xiaojie He , Indrani Paul , Benjamin Tsien , John P. Petry , Pitchaiah Katari
IPC分类号： G06F1/324 , G06F1/3237 , G06F1/3218 , G06F1/08
摘要： A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.
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公开(公告)号：US12130690B2
公开(公告)日：2024-10-29
申请号：US18316865
申请日：2023-05-12
发明人： Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC分类号： G06F1/32 , G06F1/3209 , G06F1/3234
CPC分类号： G06F1/3265 , G06F1/3209 , G06F1/3275
摘要： A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
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公开(公告)号：US12072754B2
公开(公告)日：2024-08-27
申请号：US17485199
申请日：2021-09-24
发明人： Alexander J. Branover , Christopher T. Weaver , Indrani Paul , Benjamin Tsien , Mihir Shaileshbhai Doctor , Stephen V. Kosonocky , John P. Petry , Thomas J. Gibney
IPC分类号： G06F1/00 , G06F1/3296
CPC分类号： G06F1/3296
摘要： A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.
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公开(公告)号：US11703937B2
公开(公告)日：2023-07-18
申请号：US17483698
申请日：2021-09-23
发明人： Mihir Shaileshbhai Doctor , Alexander J. Branover , Benjamin Tsien , Indrani Paul , Christopher T. Weaver , Thomas J. Gibney , Stephen V. Kosonocky , John P. Petry
IPC分类号： G06F1/32 , G06F1/3287 , G06F1/3296 , G06F1/3234
CPC分类号： G06F1/3287 , G06F1/3265 , G06F1/3278 , G06F1/3296
摘要： Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.
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公开(公告)号：US20230090126A1
公开(公告)日：2023-03-23
申请号：US17483694
申请日：2021-09-23
发明人： Benjamin Tsien , Alexander J. Branover , Christopher T. Weaver , Indrani Paul , Mihir Shaileshbhai Doctor , John P. Petry , Stephen V. Kosonocky , Thomas J. Gibney , Jose G. Cruz , Pravesh Gupta , Chintan S. Patel
IPC分类号： G06F1/3234 , G06F11/14 , G06F3/06
摘要： Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.
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公开(公告)号：US20230031388A1
公开(公告)日：2023-02-02
申请号：US17390429
申请日：2021-07-30
发明人： Benjamin Tsien , Indrani Paul , Alexander J. Branover , Thomas J. Gibney , Mihir Shaileshbhai Doctor , John P. Petry , Stephen V. Kosonocky , Christopher T. Weaver
IPC分类号： G06F1/3203
摘要： Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.
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公开(公告)号：US10120430B2
公开(公告)日：2018-11-06
申请号：US15258816
申请日：2016-09-07
发明人： Stephen V. Kosonocky , Thomas Burd , Adam Clark , Larry D. Hewitt , John Vincent Faricelli , John P. Petry
摘要： A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.
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