发明申请
- 专利标题: DEVICE AND METHOD FOR REDUCING SAVE-RESTORE LATENCY USING ADDRESS LINEARIZATION
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申请号: US17483694申请日: 2021-09-23
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公开(公告)号: US20230090126A1公开(公告)日: 2023-03-23
- 发明人: Benjamin Tsien , Alexander J. Branover , Christopher T. Weaver , Indrani Paul , Mihir Shaileshbhai Doctor , John P. Petry , Stephen V. Kosonocky , Thomas J. Gibney , Jose G. Cruz , Pravesh Gupta , Chintan S. Patel
- 申请人: Advanced Micro Devices, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F1/3234
- IPC分类号: G06F1/3234 ; G06F11/14 ; G06F3/06
摘要:
Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.
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