-
公开(公告)号：US11693089B2
公开(公告)日：2023-07-04
申请号：US17558502
申请日：2021-12-21
申请人： MEDIATEK INC.
发明人： Tzu-Chin Lin , Chih-Ming Hung , Jui-Lin Hsu , Chao-Ching Hung , Bao-Chi Peng
CPC分类号： G01S7/4021 , G01S7/4008 , G01S7/4056 , G01S13/0209 , G01S13/88 , H03J7/04 , H03J7/065 , H03L7/183 , H04B17/21
摘要： A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.
-
公开(公告)号：US20190199207A1
公开(公告)日：2019-06-27
申请号：US16137534
申请日：2018-09-20
申请人： MEDIATEK INC.
发明人： Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Po-Chun Huang
摘要： The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
-
3.发明申请公开(公告)号：US20160156361A1
公开(公告)日：2016-06-02
申请号：US14848348
申请日：2015-09-09
申请人： Mediatek Inc.
发明人： Chao-Ching Hung , Yu-Li Hsueh
CPC分类号： H03L7/16 , H03C3/0925 , H03C3/0941 , H03C3/0958 , H03L7/0891 , H03L7/099 , H03L7/0991 , H03L7/183 , H03L2207/06
摘要： A frequency synthesizing module includes an operating circuit, for generating a control voltage according to a reference signal and a feedback signal; a controllable oscillating circuit, configured for generating an oscillating signal according to the control voltage and a first control signal, comprising a first oscillating circuit with a first frequency gain, and a second oscillating circuit with a second frequency gain; a feedback circuit, for generating the feedback signal according to the oscillating signal and a second control signal; a control circuit, for generating the first control signal and the second control signal; wherein the control circuit adjusts the first control signal by a first value and adjusts the second control signal by a second value to estimate the first frequency gain of the first oscillating circuit; wherein the first value is proportional to the second value.
摘要翻译： 频率合成模块包括用于根据参考信号和反馈信号产生控制电压的操作电路; 可控振荡电路，被配置为根据所述控制电压产生振荡信号;以及第一控制信号，包括具有第一频率增益的第一振荡电路和具有第二频率增益的第二振荡电路; 反馈电路，用于根据振荡信号和第二控制信号产生反馈信号; 用于产生第一控制信号和第二控制信号的控制电路; 其中所述控制电路将所述第一控制信号调整为第一值，并且将所述第二控制信号调整为第二值以估计所述第一振荡电路的第一频率增益; 其中所述第一值与所述第二值成正比。
-
公开(公告)号：US20160118903A1
公开(公告)日：2016-04-28
申请号：US14737619
申请日：2015-06-12
申请人： MEDIATEK Inc.
发明人： Richard Y. Su , Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Yi-Chien Tsai
IPC分类号： H02M3/335
摘要： A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.
摘要翻译： 提供了包括初级电路和补偿电路的补偿装置。 初级电路提供第一电压，第二电压和流过第一电感器的第一电流。 主电路包括第一电感器和产生输入信号的功能电路。 第一电感器耦合在具有第一电压的第一端子和具有第二电压的第二端子之间。 补偿电路包括第二电感器和电流源电路。 第二电感器耦合在具有第三电压的第三端子和具有第四电压的第四端子之间。 电流源电路输出流过第二电感器的第二电流。 电流源电路调节输入信号的频率。 主电路和补偿电路通过第一电感器和第二电感器耦合。
-
公开(公告)号：US11722139B2
公开(公告)日：2023-08-08
申请号：US17575646
申请日：2022-01-14
申请人： MEDIATEK INC.
发明人： Chien-Wei Chen , Yu-Li Hsueh , Chao-Ching Hung
CPC分类号： H03L7/02 , H03L1/02 , H03L7/00 , H03L7/0995
摘要： A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.
-
公开(公告)号：US20220399897A1
公开(公告)日：2022-12-15
申请号：US17575646
申请日：2022-01-14
申请人： MEDIATEK INC.
发明人： Chien-Wei Chen , Yu-Li Hsueh , Chao-Ching Hung
IPC分类号： H03L7/099
摘要： A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.
-
公开(公告)号：US20200067405A1
公开(公告)日：2020-02-27
申请号：US16516188
申请日：2019-07-18
申请人： MEDIATEK INC.
发明人： Chao-Ching Hung , Yu-Li Hsueh , Kai-Ren Fong
IPC分类号： H02M3/07
摘要： A charge pump circuit includes first and second capacitors, first and second controllable current generating circuits, and an interconnection circuit. A first terminal of the first controllable current generating circuit is coupled to a first plate of the first capacitor. A first terminal of the second controllable current generating circuit is coupled to a first plate of the second capacitor. During a first operation mode, the first controllable current generating circuit refers to a first control input for selectively providing a first current, and the second controllable current generating circuit refers to a second control input for selectively providing a second current. During a second operation mode, the interconnection circuit couples the first plate of the second capacitor to a first power rail, and couples both of the second plate of the second capacitor and the first plate of the first capacitor to an output terminal.
-
公开(公告)号：US20190207640A1
公开(公告)日：2019-07-04
申请号：US16152391
申请日：2018-10-04
申请人： MEDIATEK INC.
发明人： Jui-Lin Hsu , Chao-Ching Hung , Tzu-Chin Lin , Wei-Hsiu Hsu , Yu-Li Hsueh , Jing-Hong Conan Zhan , Chih-Ming Hung
CPC分类号： H04B1/403 , G01S7/03 , G01S7/032 , H03B5/12 , H03B2200/008 , H03K5/135 , H04B7/2662
摘要： A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.
-
公开(公告)号：US10020777B2
公开(公告)日：2018-07-10
申请号：US15239818
申请日：2016-08-17
申请人： MEDIATEK INC.
发明人： Chao-Ching Hung , Po-Chun Huang , Yu-Li Hsueh
CPC分类号： H03B5/1234 , H03B1/00 , H03B5/06 , H03B5/10 , H03B5/1212 , H03B5/1215 , H03B2200/0094 , H03L5/00 , H03L7/099
摘要： A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.
-
公开(公告)号：US20180123575A1
公开(公告)日：2018-05-03
申请号：US15717919
申请日：2017-09-27
申请人： MEDIATEK INC.
发明人： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
CPC分类号： H03K5/15046 , H03K21/026 , H04B1/04
摘要： A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.016 秒)
