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公开(公告)号：US11601156B2
公开(公告)日：2023-03-07
申请号：US17353351
申请日：2021-06-21
Applicant: MediaTek Inc.
Inventor： Yu-Hsien Chang , Po-Chun Huang , Pi-An Wu , Wen-Hsien Chiu , Tzu-Wen Sung
Abstract: Disclosed herein are devices and methods to reduce unwanted CIM3 emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.
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公开(公告)号：US10374588B2
公开(公告)日：2019-08-06
申请号：US15717919
申请日：2017-09-27
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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公开(公告)号：US11139818B1
公开(公告)日：2021-10-05
申请号：US17124518
申请日：2020-12-17
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Yu-Li Hsueh , Chao-Ching Hung
Abstract: A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.
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公开(公告)号：US10483845B2
公开(公告)日：2019-11-19
申请号：US16137534
申请日：2018-09-20
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Po-Chun Huang
Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
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公开(公告)号：US11183971B2
公开(公告)日：2021-11-23
申请号：US17026275
申请日：2020-09-20
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Chen , Yu-Li Hsueh , Po-Chun Huang
Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.
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Patent Agency Ranking
公开(公告)号：US10020777B2
公开(公告)日：2018-07-10
申请号：US15239818
申请日：2016-08-17
Applicant: MEDIATEK INC.
Inventor： Chao-Ching Hung , Po-Chun Huang , Yu-Li Hsueh
CPC classification number: H03B5/1234 , H03B1/00 , H03B5/06 , H03B5/10 , H03B5/1212 , H03B5/1215 , H03B2200/0094 , H03L5/00 , H03L7/099
Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.
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公开(公告)号：US20180123575A1
公开(公告)日：2018-05-03
申请号：US15717919
申请日：2017-09-27
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
CPC classification number: H03K5/15046 , H03K21/026 , H04B1/04
Abstract: A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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公开(公告)号：US20170117849A1
公开(公告)日：2017-04-27
申请号：US15239818
申请日：2016-08-17
Applicant: MEDIATEK INC.
Inventor： Chao-Ching Hung , Po-Chun Huang , Yu-Li Hsueh
CPC classification number: H03B5/1234 , H03B1/00 , H03B5/06 , H03B5/10 , H03B5/1212 , H03B5/1215 , H03B2200/0094 , H03L5/00 , H03L7/099
Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.
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公开(公告)号：US11509315B2
公开(公告)日：2022-11-22
申请号：US17462014
申请日：2021-08-31
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Yu-Li Hsueh
Abstract: A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.
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公开(公告)号：US10778145B2
公开(公告)日：2020-09-15
申请号：US16681771
申请日：2019-11-12
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Po-Chun Huang , Ang-Sheng Lin , Wei-Hao Chiu
IPC: H03B5/12
Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
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