公开(公告)号：US11183971B2

公开(公告)日：2021-11-23

申请号：US17026275

申请日：2020-09-20

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Po-Chun Huang

IPC: H03B5/06 ,  G01R25/00 ,  H03B5/36 ,  H03B5/32

Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

公开(公告)号：US10809757B2

公开(公告)日：2020-10-20

申请号：US16553163

申请日：2019-08-27

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh

IPC: H03K19/096 ,  G06F1/06 ,  H03K17/687 ,  H03K19/20

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

公开(公告)号：US12113480B2

公开(公告)日：2024-10-08

申请号：US18113623

申请日：2023-02-24

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Chao-Ching Hung ,  Yu-Li Hsueh

IPC: H03B5/36 ,  H03B5/04 ,  H03B5/12

CPC classification number: H03B5/366 ,  H03B5/04 ,  H03B5/1265 ,  H03B2200/0094

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

公开(公告)号：US20240171161A1

公开(公告)日：2024-05-23

申请号：US18223537

申请日：2023-07-18

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Kairen Fong ,  Chao-Ching Hung ,  Yu-Li Hsueh

IPC: H03K5/01 ,  G04F10/00 ,  H03K3/037

CPC classification number: H03K5/01 ,  G04F10/005 ,  H03K3/037

Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.

公开(公告)号：US11671056B2

公开(公告)日：2023-06-06

申请号：US17693454

申请日：2022-03-14

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

CPC classification number: H03B5/36 ,  H03B5/362 ,  H03B5/364 ,  H03B2200/009

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

公开(公告)号：US20220069772A1

公开(公告)日：2022-03-03

申请号：US17306959

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

公开(公告)号：US20240030872A1

公开(公告)日：2024-01-25

申请号：US18113623

申请日：2023-02-24

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Chao-Ching Hung ,  Yu-Li Hsueh

IPC: H03B5/36 ,  H03B5/04 ,  H03B5/12

CPC classification number: H03B5/366 ,  H03B5/04 ,  H03B5/1265 ,  H03B2200/0094

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

公开(公告)号：US20220069773A1

公开(公告)日：2022-03-03

申请号：US17306960

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

公开(公告)号：US20200110435A1

公开(公告)日：2020-04-09

申请号：US16553163

申请日：2019-08-27

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh

IPC: G06F1/06 ,  H03K19/20 ,  H03K17/687

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

公开(公告)号：US20230117078A1

公开(公告)日：2023-04-20

申请号：US17961036

申请日：2022-10-06

Applicant: MediaTek Inc.

Inventor： Cheng-Yi Chang ,  Yi-Chun Chou ,  Ching-Wen Hsiao ,  Chien-Wei Chen

IPC: H04W52/02 ,  H04W52/42

Abstract: Techniques pertaining to low-power enhanced multi-link single radio (EMLSR) listen in wireless communications are described. A first multi-link device (MLD) reduces power consumption while supporting a latency-sensitive application by performing certain operations. The first MLD first listens at a lower power in a narrower bandwidth to receive an initial physical-layer protocol data unit (PPDU) from a second MLD as part of a frame exchange. In response to receiving the initial PPDU, the first MLD switches from the narrower bandwidth to a wider bandwidth to complete the frame exchange with the second MLD in the wider bandwidth. In reducing the power consumption, the first MLD reduces its power consumption to the lower power when operating in the narrower bandwidth compared to a higher power used by the first MLD when operating in the wider bandwidth.