公开(公告)号：US20240171438A1

公开(公告)日：2024-05-23

申请号：US18515311

申请日：2023-11-21

Applicant: MediaTek Inc.

Inventor： Shengquan Hu ,  Ching-Wen Hsiao ,  Jianhan Liu ,  Thomas Edward Pare, JR.

IPC: H04L27/26 ,  H04L5/00

CPC classification number: H04L27/2613 ,  H04L5/0007 ,  H04L5/0048

Abstract: Various schemes pertaining to long training field (LTF) and short training field (STF) transmission for wide bandwidth 240 MHz with more direct-current (DC) tones in wireless communications are described. A processor of an apparatus generates either or both of an LTF and a STF of a physical-layer protocol data unit (PPDU) with a center 996-tone resource unit (RU) having more than a predetermined number of DC tones. The processor then performs a wireless communication in a wide bandwidth (e.g., 240 MHz) with the PPDU.

公开(公告)号：US10692789B2

公开(公告)日：2020-06-23

申请号：US15968449

申请日：2018-05-01

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

公开(公告)号：US10177125B2

公开(公告)日：2019-01-08

申请号：US15618210

申请日：2017-06-09

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

IPC: H01L25/16 ,  H01L25/10 ,  H01L23/485 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498

Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.

公开(公告)号：US20180323127A1

公开(公告)日：2018-11-08

申请号：US15968449

申请日：2018-05-01

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

公开(公告)号：US09711488B2

公开(公告)日：2017-07-18

申请号：US15014604

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/053 ,  H01L21/30 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.

公开(公告)号：US20170053884A1

公开(公告)日：2017-02-23

申请号：US15182581

申请日：2016-06-14

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14134 ,  H01L2224/14153 ,  H01L2224/14177 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19102 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.

Abstract translation: 用于集成电路封装的球栅阵列包括源自在集成电路封装的至少一个或多个部分中重复的六边形图案的基本单元的连接点阵列。 根据一个实施例，连接点是安装在集成电路封装的下表面上的焊球。

公开(公告)号：US20240129081A1

公开(公告)日：2024-04-18

申请号：US18376697

申请日：2023-10-04

Applicant: MediaTek Inc.

Inventor： Shengquan Hu ,  Ching-Wen Hsiao ,  Jianhan Liu ,  Thomas Edward Pare, Jr.

IPC: H04L5/00

CPC classification number: H04L5/0044 ,  H04L5/0094

Abstract: Various schemes pertaining to center 996-tone resource unit (RU996) tone plan designs for wide bandwidth 240 MHz in wireless communications are described. A communication entity generates at least one 996-tone resource unit (RU996). The communication entity then communicates wirelessly using the at least one RU996 in a 240 MHz bandwidth. The at least one RU996 includes a center RU996 that is centered around five or more direct-current (DC) tones.

公开(公告)号：US10483211B2

公开(公告)日：2019-11-19

申请号：US15418896

申请日：2017-01-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Nai-Wei Liu ,  Wei-Che Huang

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

公开(公告)号：US10217724B2

公开(公告)日：2019-02-26

申请号：US15047980

申请日：2016-02-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H05K1/18

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

公开(公告)号：US20230117111A1

公开(公告)日：2023-04-20

申请号：US17964876

申请日：2022-10-12

Applicant: MediaTek Inc.

Inventor： Cheng-Yi Chang ,  Ching-Wen Hsiao ,  Shu-Ping Shiu

IPC: H04W76/15 ,  H04W52/02

Abstract: Techniques pertaining to coverage enhancement for 6 GHz wireless communications are described. A first station (STA) communicates with a second STA in a 6 GHz wireless band and/or low-power indoor (LPI) channels. The first STA performs a receiving signal combination and detection across multiple bandwidths such that a power level or a signal strength is enhanced in communicating with the second STA.