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    Mixed signal device with different pluralities of digital cells
    1.
    发明授权
    Mixed signal device with different pluralities of digital cells 有权

    公开(公告)号：US12021526B2

    公开(公告)日：2024-06-25

    申请号：US17684098

    申请日：2022-03-01

    Applicant: Sandeep Kumar Gupta

    Inventor： Sandeep Kumar Gupta

    IPC: H03K19/08 ,  H03K19/0185 ,  H03K19/17784 ,  H03K19/20

    CPC classification number: H03K19/0813 ,  H03K19/018585 ,  H03K19/17784 ,  H03K19/20

    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

    Method of obfuscating digital logic circuits using threshold voltage
    6.
    发明授权
    Method of obfuscating digital logic circuits using threshold voltage 有权

    公开(公告)号：US09876503B2

    公开(公告)日：2018-01-23

    申请号：US15390970

    申请日：2016-12-27

    Applicant: Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

    Inventor： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

    IPC: H03K19/20 ,  H03K19/08 ,  H03K19/096 ,  H03K19/21

    CPC classification number: H03K19/0813 ,  H03K19/0963 ,  H03K19/21

    Abstract: A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

    Multi-threshold circuitry based on silicon-on-insulator technology
    7.
    发明授权
    Multi-threshold circuitry based on silicon-on-insulator technology 有权
    基于绝缘体上硅技术的多阈值电路

    公开(公告)号：US09257984B2

    公开(公告)日：2016-02-09

    申请号：US14487678

    申请日：2014-09-16

    Applicant: Wave Semiconductor, Inc.

    Inventor： Gajendra Prasad Singh ,  Roger Carpenter

    IPC: H01L27/10 ,  H03K19/0948 ,  H01L27/12 ,  G06F17/50 ,  H01L21/84 ,  H03K19/08 ,  H03K19/20

    CPC classification number: H03K19/0948 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/84 ,  H01L27/1203 ,  H03K19/0813 ,  H03K19/20

    Abstract: Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.

    Abstract translation: 公开了基于绝缘体上硅（SOI）技术的多阈值电压电路，其利用SOI FET中的绝缘体下方的N阱和/或P阱。 FET下的阱被偏置以影响FET的阈值电压。 PFET和NFET共享一个普通的P阱或N阱。 可以使用多个阈值电压FET在绝缘体上硅（SOI）技术中制造各种类型的逻辑。 实施例提供了包括低泄漏晶体管和高速晶体管的有利特性的电路。

    ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN
    8.
    发明申请
    ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN 失效
    超低功耗多路非同步电路设计

    公开(公告)号：US20120133390A1

    公开(公告)日：2012-05-31

    申请号：US13175168

    申请日：2011-07-01

    Applicant: Jia Di ,  Scott Christopher Smith

    Inventor： Jia Di ,  Scott Christopher Smith

    IPC: H03K19/23

    CPC classification number: H03K19/0016 ,  H03K19/0813

    Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

    Abstract translation: 多阈值CMOS NULL约定逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。 四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

    THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE
    9.
    发明申请
    THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE 有权
    具有低泄漏功率和高性能的阈值逻辑元件

    公开(公告)号：US20100321061A1

    公开(公告)日：2010-12-23

    申请号：US12867352

    申请日：2009-02-13

    Applicant: Samuel Leshner ,  Sarma Vrudhula

    Inventor： Samuel Leshner ,  Sarma Vrudhula

    IPC: H03K19/23

    CPC classification number: H03K19/0813

    Abstract: Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.

    Abstract translation: 提供了阈值逻辑元件的实施例。 优选地，本文所讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。 在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可提供快速有效的数字逻辑功能实现。 TLL可以同步或异步操作，并且与标准互补金属氧化物半导体（CMOS）技术完全兼容。

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