公开(公告)号：US20120133390A1

公开(公告)日：2012-05-31

申请号：US13175168

申请日：2011-07-01

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/23

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract translation: 多阈值CMOS NULL约定逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。 四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

公开(公告)号：US20130181740A1

公开(公告)日：2013-07-18

申请号：US13739778

申请日：2013-01-11

Applicant: Scott Christopher Smith ,  Jia Di

Inventor： Scott Christopher Smith ,  Jia Di

IPC: H03K19/173

CPC classification number: H03K19/173 ,  H03K19/0016 ,  H03K19/0963

Abstract: A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.

Abstract translation: 静态休眠约定逻辑（SSCL）电路。 该电路改进了在多阈值空会计逻辑（MTNCL），在美国专利中公开。 No. 7,977,972通过利用SECRII架构以及Bit-Wise MTNCL技术，生产一个没有nsleep输入的新型SSCL门，这样就产生了一个更小更快的电路，每个操作的能量都比专利的SMTNCL门设计少，而 睡眠模式下泄漏功率只有非常轻微的增加。

公开(公告)号：US09083337B2

公开(公告)日：2015-07-14

申请号：US13739778

申请日：2013-01-11

Applicant: Scott Christopher Smith ,  Jia Di

Inventor： Scott Christopher Smith ,  Jia Di

IPC: H03K19/173 ,  H03K19/00 ,  H03K19/096

CPC classification number: H03K19/173 ,  H03K19/0016 ,  H03K19/0963

Abstract: A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.

Abstract translation: 静态休眠约定逻辑（SSCL）电路。 该电路改进了在多阈值空会计逻辑（MTNCL），在美国专利中公开。 No. 7,977,972通过利用SECRII架构以及Bit-Wise MTNCL技术，生产一个没有nsleep输入的新型SSCL门，这样就产生了一个更小更快的电路，每个操作的能量都比专利的SMTNCL门设计少，而 睡眠模式下泄漏功率只有非常轻微的增加。

公开(公告)号：US08664977B2

公开(公告)日：2014-03-04

申请号：US13479706

申请日：2012-05-24

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/20

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

Abstract translation: 多阈值零约定逻辑电路。 该电路包括第一电路，耦合到Vcc的第一高阈值晶体管和从第一电路驱动的第一高阈值晶体管的功率的逆变器，并且包括输出。

公开(公告)号：US20120293198A1

公开(公告)日：2012-11-22

申请号：US13479706

申请日：2012-05-24

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/003 ,  H05K13/00

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

Abstract translation: 多阈值零约定逻辑电路。 该电路包括第一电路，耦合到Vcc的第一高阈值晶体管和从第一电路驱动的第一高阈值晶体管的功率的逆变器，并且包括输出。

公开(公告)号：US08207758B2

公开(公告)日：2012-06-26

申请号：US13175168

申请日：2011-07-01

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/20

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract translation: 多阈值CMOS NULL约定逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。 四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

公开(公告)号：US07977972B2

公开(公告)日：2011-07-12

申请号：US12771886

申请日：2010-04-30

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/173

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract translation: 多阈值CMOS NULL逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。 四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

公开(公告)号：US20110032000A1

公开(公告)日：2011-02-10

申请号：US12771886

申请日：2010-04-30

Applicant: Jia Di ,  Scott Christopher Smith

Inventor： Jia Di ,  Scott Christopher Smith

IPC: H03K19/096 ,  H03K19/00

CPC classification number: H03K19/0016 ,  H03K19/0813

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract translation: 多阈值CMOS NULL约定逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。 四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

公开(公告)号：US11095287B1

公开(公告)日：2021-08-17

申请号：US16937670

申请日：2020-07-24

Applicant: Jia Di ,  Chandler Bernard

Inventor： Jia Di ,  Chandler Bernard

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/21 ,  H03K19/0944

Abstract: Multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage.

公开(公告)号：US10804903B1

公开(公告)日：2020-10-13

申请号：US16684961

申请日：2019-11-15

Applicant: Jia Di ,  Andrew Lloyd Suchanek ,  Zhong Chen ,  Matthew Leftwich

Inventor： Jia Di ,  Andrew Lloyd Suchanek ,  Zhong Chen ,  Matthew Leftwich

IPC: H03K19/17784 ,  H03K19/17788 ,  H03K19/08

Abstract: A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.