公开(公告)号：US09876503B2

公开(公告)日：2018-01-23

申请号：US15390970

申请日：2016-12-27

Applicant: Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

Inventor： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

IPC: H03K19/20 ,  H03K19/08 ,  H03K19/096 ,  H03K19/21

CPC classification number: H03K19/0813 ,  H03K19/0963 ,  H03K19/21

Abstract: A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

公开(公告)号：US07539961B2

公开(公告)日：2009-05-26

申请号：US11601573

申请日：2006-11-17

Applicant: Enis Aykut Dengi ,  Feng Ling ,  Ben Song ,  Warren Harris

Inventor： Enis Aykut Dengi ,  Feng Ling ,  Ben Song ,  Warren Harris

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5036 ,  G06F17/5045

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract translation: 用于对IC（集成电路）进行建模的系统和方法使用网格模型和网格模型来分离近距离和远距离的网格元素对之间的阻抗效应。 用于相关电流和电压的模型可以在包括混合信号，模拟和RF（射频）电路的应用中的其他设计或设计元件中逐渐适应。

公开(公告)号：US07356784B1

公开(公告)日：2008-04-08

申请号：US11006323

申请日：2004-12-06

Applicant: Enis Aykut Dengi ,  Stephen McCracken ,  Michael R. Kelly ,  Matthew B. Phelps ,  Ibraz Mohammed

Inventor： Enis Aykut Dengi ,  Stephen McCracken ,  Michael R. Kelly ,  Matthew B. Phelps ,  Ibraz Mohammed

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036

Abstract: A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from the one or more device variables and the one or more weights; and determining the IC design from the one or more device variables and the one or more net lengths. The IC design includes a schematic and a layout. The process can be repeated as needed according to performance criteria that may include circuit performance metrics and layout performance metrics.

Abstract translation: 确定IC（集成电路）设计的方法包括：确定一个或多个设计变量，其中所述一个或多个设计变量包括一个或多个设备变量和一个或多个权重; 从所述一个或多个设备变量和所述一个或多个权重确定一个或多个净长度和一个或多个布局度量; 以及从所述一个或多个设备变量和所述一个或多个净长度确定所述IC设计。 IC设计包括原理图和布局。 根据可能包括电路性能指标和布局性能指标的性能标准，可以根据需要重复该过程。

公开(公告)号：US20210304421A1

公开(公告)日：2021-09-30

申请号：US17306148

申请日：2021-05-03

Applicant: Abraham Othman ,  Enis Aykut Dengi ,  Ishan Agrawal ,  Jeff Kershner ,  Peter Martinez ,  Paul Mills ,  Abhinav Yarlagadda

Inventor： Abraham Othman ,  Enis Aykut Dengi ,  Ishan Agrawal ,  Jeff Kershner ,  Peter Martinez ,  Paul Mills ,  Abhinav Yarlagadda

IPC: G06T7/292 ,  G06K9/00 ,  H04N7/18 ,  G06T7/246 ,  G06Q30/02 ,  G06Q30/06

Abstract: A visual tracking system for tracking and identifying persons within a monitored location, comprising a plurality of cameras and a visual processing unit, each camera produces a sequence of video frames depicting one or more of the persons, the visual processing unit is adapted to maintain a coherent track identity for each person across the plurality of cameras using a combination of motion data and visual featurization data, and further determine demographic data and sentiment data using the visual featurization data, the visual tracking system further having a recommendation module adapted to identify a customer need for each person using the sentiment data of the person in addition to context data, and generate an action recommendation for addressing the customer need, the visual tracking system is operably connected to a customer-oriented device configured to perform a customer-oriented action in accordance with the action recommendation.

公开(公告)号：US07506294B2

公开(公告)日：2009-03-17

申请号：US11601601

申请日：2006-11-17

Applicant: Enis Aykut Dengi ,  Feng Ling ,  Ben Song ,  Warren Harris

Inventor： Enis Aykut Dengi ,  Feng Ling ,  Ben Song ,  Warren Harris

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract translation: 用于对IC（集成电路）进行建模的系统和方法使用网格模型和网格模型来分离近距离和远距离的网格元素对之间的阻抗效应。 用于相关电流和电压的模型可以在包括混合信号，模拟和RF（射频）电路的应用中的其他设计或设计元件中逐渐适应。

公开(公告)号：US07139987B2

公开(公告)日：2006-11-21

申请号：US10618237

申请日：2003-07-11

Applicant: Gang Zhang ,  Enis Aykut Dengi ,  Ronald A. Rohrer

Inventor： Gang Zhang ,  Enis Aykut Dengi ,  Ronald A. Rohrer

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5063

Abstract: In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.

Abstract translation: 在自动集成电路设计中，如果电路装置的布局的性能不在规定的性能规格公差范围内，则电路装置中的至少一个被调整大小或重新定位，并且每个重新定位或重新定位的电路的装置参数的更新值 设备确定。 然后确定每个设备参数的初始值和更新值之间的差异，并且将每个差值与由设备参数之一的值的变化和受设备参数影响的性能的值的变化形成的比率组合 。 然后将该组合的结果与性能的初始值相结合以确定其更新的值。

公开(公告)号：US10551869B2

公开(公告)日：2020-02-04

申请号：US15443444

申请日：2017-02-27

Applicant: Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni

Inventor： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni

IPC: G06F1/12 ,  G06F1/10

Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

公开(公告)号：US07957949B1

公开(公告)日：2011-06-07

申请号：US12685605

申请日：2010-01-11

Applicant: Pero Subasic ,  Enis Aykut Dengi

Inventor： Pero Subasic ,  Enis Aykut Dengi

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5045 ,  Y10S706/921

Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.

Abstract translation: 一种系统设计的方法，更具体地说，一种设计使用分层分区系统表示实现一组性能目标的系统的方法，其中性能模拟在层级内的多个级别执行并被组合以模拟系统级结果，以便 减少性能仿真所需的总时间。

公开(公告)号：US07127688B2

公开(公告)日：2006-10-24

申请号：US10837293

申请日：2004-04-30

Applicant: Feng Ling ,  Vladimir I. Okhmatovski ,  Enis Aykut Dengi

Inventor： Feng Ling ,  Vladimir I. Okhmatovski ,  Enis Aykut Dengi

IPC: G06F17/50 ,  G06F19/00 ,  G01R19/00

CPC classification number: G06F17/5018 ,  G06F17/5036 ,  G06F2217/78

Abstract: To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer is determined from the scalar charge elements in all of the circuit layers. For each circuit layer, the first and second distributions of voltages induced therein are combined to determine an actual distribution of voltages in the circuit layer.

Abstract translation: 为了估计多层电路层中的电压或电流的分​​布，每层中的示例性电流流离散化为多个电流矢量元素，以及与每个电流矢量相关的电荷相关的至少一个标量电荷元素 元件。 在每个电路层中感应的电压的第一分布由所有电路层中的电流矢量元素确定。 在每个电路层中感应的电压的第二分布由所有电路层中的标量电荷元素确定。 对于每个电路层，其中感应的电压的第一和第二分布被组合以确定电路层中的电压的实际分布。

公开(公告)号：US06500723B1

公开(公告)日：2002-12-31

申请号：US09972397

申请日：2001-10-05

Applicant: Michael G. Khazhinsky ,  Aykut Dengi ,  James W. Miller

Inventor： Michael G. Khazhinsky ,  Aykut Dengi ,  James W. Miller

IPC: H01L2120

CPC classification number: H01L28/20 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/74 ,  H01L27/0288 ,  H01L27/0802 ,  Y10S438/947

Abstract: A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Abstract translation: 使用与用于常规孔的光致抗蚀剂和植入步骤相同的掩模形成隔离层下面的许多小孔。 小孔形成得足够接近，使得它们在正常的后续半导体处理期间合并以形成合并井。 正常井和小井的浓度大于合并井的浓度。 通过确保小井足够靠近，使得从正在使用的特定半导体工艺发生的井注入的正常扩散导致合并，确保小井的期望合并。 与掺杂浓度较低的合并井的一个理想用途是作为电阻器，具有比常规阱更多的电阻，而不需要额外的注入。