公开(公告)号：US20230178869A1

公开(公告)日：2023-06-08

申请号：US18072851

申请日：2022-12-01

申请人： Silergy Semiconductor Technology (Hangzhou) LTD

发明人： Chiqing Wang ,  Wei Chen ,  Yufei Dong ,  Xiaodong Huang ,  Chen Zhao

IPC分类号： H01P1/36 ,  H03M5/16

CPC分类号： H01P1/36 ,  H03M5/16

摘要： A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to encode a rising edge and a falling edge of the input digital signal into different coded signals; an isolating element coupled to encoding circuit, and being configured to transmit the coded signal in an electrical isolation manner; and a decoding circuit configured to receive the coded signal through the isolation element, and to decode the coded signal to obtain the rising edge and the falling edge, in order to output an output digital signal consistent with the input digital signal, where the rising edge of the input digital signal is encoded as a first pulse sequence, and the falling edge of the input digital signal is encoded as a second pulse sequence different from the first pulse sequence.

公开(公告)号：US09686107B2

公开(公告)日：2017-06-20

申请号：US15169446

申请日：2016-05-31

申请人： Kandou Labs, S.A.

发明人： John Fox ,  Brian Holden ,  Peter Hunt ,  John D. Keay ,  Amin Shokrollahi ,  Richard Simpson ,  Anant Singh ,  Andrew Kevin John Stewart ,  Giuseppe Surace

IPC分类号： H04L25/49 ,  H04L25/493 ,  H04L25/02 ,  H03M5/16 ,  H03M5/20 ,  G06F13/42 ,  H04L29/06

CPC分类号： H04L25/4906 ,  G06F13/426 ,  H03M5/16 ,  H03M5/20 ,  H04L25/0272 ,  H04L25/4917 ,  H04L25/493 ,  H04L69/04 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

公开(公告)号：US09124557B2

公开(公告)日：2015-09-01

申请号：US14158452

申请日：2014-01-17

申请人： Kandou Labs, S.A.

发明人： John Fox ,  Brian Holden ,  Peter Hunt ,  John D. Keay ,  Amin Shokrollahi ,  Richard Simpson ,  Anant Singh ,  Andrew Kevin John Stewart ,  Giuseppe Surace

IPC分类号： H03M5/16 ,  H03M5/20 ,  H04L29/06 ,  H04L25/49

CPC分类号： H04L25/4906 ,  G06F13/426 ,  H03M5/16 ,  H03M5/20 ,  H04L25/0272 ,  H04L25/4917 ,  H04L25/493 ,  H04L69/04 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

摘要翻译： 描述了用于通过物理信道传输数据的系统和方法，以提供高速，低延迟的接口，例如在显着减少或消除的同时开关输出噪声的存储器控​​制器和存储器件之间。 公开了这样的信道接口的控制器侧和存储器侧实施例，其不需要额外的引脚数或数据传输周期，具有低功率利用率，并且引入最小的附加等待时间。 在本发明的一些实施例中，三个或更多个电压电平用于信令。

公开(公告)号：US09015566B2

公开(公告)日：2015-04-21

申请号：US14028240

申请日：2013-09-16

申请人： École Polytechnique Fédérale de Lausanne (EPFL)

发明人： Harm Cronie ,  Amin Shokrollahi

IPC分类号： G06F11/00 ,  H04L1/00 ,  H03M5/04 ,  H03M5/16 ,  H03M13/31

CPC分类号： H04L1/0041 ,  H03M5/04 ,  H03M5/16 ,  H03M13/31 ,  H04L1/0057 ,  H04L2001/0094

摘要： In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

摘要翻译： 在总线通信方法和装置中，提供表示要通过总线传送的信息的第一组物理信号，并将其映射到球码的码字，其中码字可表示为多个分量的向量，并且 总线使用至少与所使用的向量的分量相同的信号线，将码字映射到第二组物理信号，其中第二组物理信号的分量可以具有来自具有至少三个的组分值的集合的值 提供用于至少一个组件的不同值，以及提供第二组物理信号，以便以物理形式在数据总线上传输。

公开(公告)号：US07990292B2

公开(公告)日：2011-08-02

申请号：US12111125

申请日：2008-04-28

申请人： Dirk Marien

发明人： Dirk Marien

IPC分类号： H03M5/16 ,  H03M7/12

CPC分类号： G06F21/606

摘要： The invention relates to a method to efficiently transmit a digital message over a unidirectional optical link, such as the link between a computer screen and a security token equipped with photosensitive elements. It is an object of this invention to provide a source coding scheme that is optimized for transmissions of alphanumerical data containing frequent occurrences of numerals and less frequent occurrences of non-numerical data. This is achieved by using a modified Huffman code for source coding, consisting of a nibble-based prefix-free binary code. The output of the coder is efficiently mapped onto a 6B4T channel code, wherein unused ternary codewords can be used to signal data-link layer events. This efficient signalling of data-link layer events, in turn, allows for a synchronization scheme based on repeated transmissions of a finite-length message, combined with an out-of-band clock signal.

摘要翻译： 本发明涉及一种通过诸如计算机屏幕和装备有感光元件的安全令牌之间的链接的单向光学链路来有效地发送数字消息的方法。 本发明的一个目的是提供一种源代码编码方案，该方案针对包含频繁出现的数字的字母数字数据的传输进行优化，并且不频繁出现非数字数据。 这通过使用用于源编码的修改的霍夫曼码来实现，该编码由基于半字节的前缀无二进制码组成。 编码器的输出被有效地映射到6B4T信道码，其中未使用的三进制码字可以用于信号数据链路层事件。 数据链路层事件的这种有效的信令反过来允许基于与带外时钟信号组合的有限长度消息的重复传输的同步方案。

公开(公告)号：US20090045988A1

公开(公告)日：2009-02-19

申请号：US12188261

申请日：2008-08-08

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03M5/16

CPC分类号： H04L9/0662 ,  H04L2209/12

摘要： A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

摘要翻译： 一种用于将多个m状态符号的消息编码成n状态符号的编码消息的方法，其中n> m被公开。 还公开了使n态符号的状态分布均匀分布的方法。 基于m状态符号的状态分布来启动编码规则。 还提供了通过转置编码编码规则的方法。 在一个实施例中，n状态符号的编码消息具有每个具有独特状态的符号。 还公开了一种用于执行编码和解码方法的系统。

公开(公告)号：US6040709A

公开(公告)日：2000-03-21

申请号：US82561

申请日：1998-05-21

申请人： Kazunori Kishimoto

发明人： Kazunori Kishimoto

IPC分类号： H03M5/16 ,  H04L25/49 ,  H03K19/01 ,  H03K19/02

CPC分类号： H03M5/16

摘要： A ternary signal input circuit includes two inverters having opposite hysteresis characteristics, respectively, a NOR gate for producing an output signal indicative of an inversion of the logical sum of output signals from the inverters, and a AND gate for producing an output signal indicative of the logical product of output signals from the inverters. The ternary signal input circuit, composed only of digital components, converts a ternary signal supplied through a transformer into binary signals and outputs the binary signals. The ternary signal input circuit has a relatively simple circuit arrangement and will take up a relatively small area on an LSI chip when it is incorporated into the LSI chip.

摘要翻译： 三态信号输入电路分别包括具有相反磁滞特性的两个反相器，NOR门，用于产生指示来自反相器的输出信号的逻辑和的反相的输出信号;以及与门，用于产生指示 来自逆变器的输出信号的逻辑积。 由数字组件组成的三态信号输入电路将通过变压器提供的三态信号转换为二进制信号并输出​​二进制信号。 三元信号输入电路具有相对简单的电路布置，并且当其被并入LSI芯片时将占据LSI芯片上相对较小的面积。

公开(公告)号：US5912563A

公开(公告)日：1999-06-15

申请号：US862132

申请日：1997-05-22

申请人： Paul Jeffrey Garnett

发明人： Paul Jeffrey Garnett

IPC分类号： H03K19/20 ,  H03M5/16 ,  H04L25/49 ,  H03K19/00

CPC分类号： H03M5/16 ,  H04L25/4923

摘要： Extended trinary signal apparatus includes window comparator logic having first and second inputs for first and second trinary input signals, wherein each the trinary input signal can be a high, low or mid state, and an output for outputting signals dependent on the states of the first and second trinary input signals. A switch, which is connected to one of the first and second inputs, can be selectively activated in one phase to set the one of the first and second inputs to a state other than the mid state and can be inactive in another phase. Control logic is responsive to output signals from the window comparator output during the one and the other phase to provide extended trinary decoding of the trinary input signals. In this manner ninth and tenth input combinations can be identified by detecting whether two inputs which show a mid state are electrically connected to each other or not, this being achieved by selectively pulling one of the inputs to a predetermined state and determining whether the other input follows or not. Trinary encoding can thus be extended to provide ten, rather than the conventional nine states from two inputs.

摘要翻译： 扩展三态信号装置包括窗口比较器逻辑，其具有用于第一和第二三进制输入信号的第一和第二输入，其中每个三进制输入信号可以是高，低或中等状态，以及用于输出取决于第一和第二三态输入信号的状态的信号的输出 和第二三进制输入信号。 连接到第一和第二输入中的一个的开关可以在一个相位中选择性地激活，以将第一和第二输入中的一个设置为除了中间状态之外的状态，并且可以在另一个阶段中不起作用。 在一个和另一个相位期间，控制逻辑响应来自窗口比较器输出的输出信号，以提供三进制输入信号的扩展三进制解码。 以这种方式，可以通过检测表示中间状态的两个输入是否彼此电连接来识别第九和第十输入组合，这通过选择性地将输入中的一个拉到预定状态并确定另一个输入 遵循与否 因此，可以扩展三进制编码，以从两个输入提供十个而不是常规的九个状态。

公开(公告)号：US5892858A

公开(公告)日：1999-04-06

申请号：US827419

申请日：1997-03-27

申请人： Mazoud Vaziri ,  Maurice S. O'Sullivan ,  Terry W. B. Taraschuk ,  Alan Glen Solheim ,  Kim Byron Roberts

发明人： Mazoud Vaziri ,  Maurice S. O'Sullivan ,  Terry W. B. Taraschuk ,  Alan Glen Solheim ,  Kim Byron Roberts

IPC分类号： G02F1/01 ,  H03M5/16 ,  H03M5/18 ,  H04B10/00 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152 ,  H04B10/155 ,  H04L25/497 ,  G02B6/10

CPC分类号： H04B10/5055 ,  H03M5/18 ,  H04B10/505 ,  H04B10/5167

摘要： A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit y.sub.k =0 when the corresponding bit x.sub.k =0; bits y.sub.k alternatively assume a logical level "+1" and "-1" whenever an input bit x.sub.k-1 =0 changes to x.sub.k =1, and the output bit y.sub.k maintains the logical level "+1" or "-1" whenever the corresponding bit x.sub.k maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving a M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.

摘要翻译： 提供了一种用于对二进制输入序列x（0,1）进行编码以获得双二进制输出序列y（+ 1,0，-1）的方法。 当对应的位xk = 0时，双向编码技术总是提供输出位yk = 0; 只要输入位xk-1 = 0改变为xk = 1，位yk或者假设逻辑电平“+1”和“-1”，并且输出位yk每当维持逻辑电平“+1”或“-1” 对应的位xk保持逻辑电平“1”。 还提供了用于将二进制输入序列x（0,1）编码到二进制输出序列y（+ 1,0，-1）的编码装置，包括用于产生二进制开关信号的D型触发器。 第一AND电路接收输入序列和开关信号，并提供第一二进制序列a（0,1），而第二AND电路接收输入序列和开关信号的补码，并提供第二二进制序列b（ 0,1）。 将这些第一和第二二进制序列应用于加法器以获得输出序列y（+ 1,0，-1）。 还提供了一种用于使用虚拟接地电平差分驱动M-Z调制器的方法，其将峰 - 峰驱动电压降低了二倍。

公开(公告)号：US5828228A

公开(公告)日：1998-10-27

申请号：US921568

申请日：1997-09-02

申请人： Karl M. Fant ,  Scott A. Brandt

发明人： Karl M. Fant ,  Scott A. Brandt

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  G06F11/08 ,  H03K19/08 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16 ,  H03K19/00

CPC分类号： G06F7/502 ,  G06F11/085 ,  G06F7/00 ,  G06F7/5052 ,  H03K19/0813 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16 ,  G06F2207/4822

摘要： A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The output produces output NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The threshold switching circuit triggers changes of the output signal state to NULL in response to the states of all the input signals becoming NULL. The threshold switching circuit triggers changes of the output signal state to the meaningful state when the number of the input signals in the meaningful state exceeds a threshold number. The threshold switching circuit triggers changes of the output signal state to the third state when (i) fewer than all input signals are in the NULL state, and (ii) fewer than the threshold number of input signals are in the meaningful state.

摘要翻译： 空常规逻辑元件包括输入，输出和阈值切换电路。 该输入接收被编码到多个物理输入信号线上的NULL约定信号，该多个物理输入信号线可以呈现指示数据的至少第一有意义的信号状态，不具有逻辑含义的空信号状态和与第一和第二信号不同的第三信号状态 状态。 该输出产生编码到多个物理输入信号线上的输出NULL约定信号，该多个物理输入信号线可以呈现指示数据的至少第一有意义的信号状态，不具有逻辑含义的空信号状态和与第一和第二 信号状态。 响应于所有输入信号变为NULL的状态，阈值切换电路将输出信号状态的改变触发为NULL。 当有意义状态的输入信号的数量超过阈值时，阈值切换电路将输出信号状态的变化触发到有意义的状态。 当（i）少于所有输入信号处于空状态时，阈值切换电路触发输出信号状态的变化到第三状态，并且（ii）少于阈值数量的输入信号处于有意义的状态。