公开(公告)号：US5892858A

公开(公告)日：1999-04-06

申请号：US827419

申请日：1997-03-27

申请人： Mazoud Vaziri ,  Maurice S. O'Sullivan ,  Terry W. B. Taraschuk ,  Alan Glen Solheim ,  Kim Byron Roberts

发明人： Mazoud Vaziri ,  Maurice S. O'Sullivan ,  Terry W. B. Taraschuk ,  Alan Glen Solheim ,  Kim Byron Roberts

IPC分类号： G02F1/01 ,  H03M5/16 ,  H03M5/18 ,  H04B10/00 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152 ,  H04B10/155 ,  H04L25/497 ,  G02B6/10

CPC分类号： H04B10/5055 ,  H03M5/18 ,  H04B10/505 ,  H04B10/5167

摘要： A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit y.sub.k =0 when the corresponding bit x.sub.k =0; bits y.sub.k alternatively assume a logical level "+1" and "-1" whenever an input bit x.sub.k-1 =0 changes to x.sub.k =1, and the output bit y.sub.k maintains the logical level "+1" or "-1" whenever the corresponding bit x.sub.k maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving a M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.

摘要翻译： 提供了一种用于对二进制输入序列x（0,1）进行编码以获得双二进制输出序列y（+ 1,0，-1）的方法。 当对应的位xk = 0时，双向编码技术总是提供输出位yk = 0; 只要输入位xk-1 = 0改变为xk = 1，位yk或者假设逻辑电平“+1”和“-1”，并且输出位yk每当维持逻辑电平“+1”或“-1” 对应的位xk保持逻辑电平“1”。 还提供了用于将二进制输入序列x（0,1）编码到二进制输出序列y（+ 1,0，-1）的编码装置，包括用于产生二进制开关信号的D型触发器。 第一AND电路接收输入序列和开关信号，并提供第一二进制序列a（0,1），而第二AND电路接收输入序列和开关信号的补码，并提供第二二进制序列b（ 0,1）。 将这些第一和第二二进制序列应用于加法器以获得输出序列y（+ 1,0，-1）。 还提供了一种用于使用虚拟接地电平差分驱动M-Z调制器的方法，其将峰 - 峰驱动电压降低了二倍。