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公开(公告)号:US20240289668A1
公开(公告)日:2024-08-29
申请号:US18455929
申请日:2023-08-25
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Hayato GOTO
Abstract: According to one embodiment, an encoder includes a first element part and a controller. The first element part includes a first qubit, a second qubit couplable with the first qubit, a third qubit couplable with the second qubit, a fourth qubit couplable with the third qubit, a fifth qubit couplable with the fourth qubit, a sixth qubit couplable with the fifth qubit, a seventh qubit couplable with the sixth qubit, an eighth qubit couplable with the seventh qubit, and a ninth qubit couplable with the eighth qubit. The controller is configured to perform a first control. The first control includes encoding a surface code having a code distance of 3.
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公开(公告)号:US11764805B2
公开(公告)日:2023-09-19
申请号:US17533014
申请日:2021-11-22
Applicant: Samsung Display Co., Ltd.
Inventor: Aliazam Abbasfar
CPC classification number: H03M7/46 , G06F9/30029 , H03M5/145 , H04L7/0016 , H03M13/31
Abstract: A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.
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公开(公告)号:US11496155B2
公开(公告)日:2022-11-08
申请号:US17224064
申请日:2021-04-06
Applicant: Codelucida, Inc.
Inventor: David Declercq , Vamsi Krishna Yella , Benedict J. Reynwar
Abstract: A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.
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公开(公告)号:US11374801B2
公开(公告)日:2022-06-28
申请号:US16143228
申请日:2018-09-26
Applicant: Kandou Labs, S.A.
Inventor: John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
IPC: H04L25/02 , H01Q13/24 , H01Q13/28 , H01R12/00 , H04L25/08 , H04L25/14 , H04L25/03 , H04L25/49 , H04L5/02 , H04L27/01 , H01L29/768 , G01R31/3183 , H03M5/04 , H03M5/16 , H03M13/31 , H04L1/00
Abstract: A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.
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5.
公开(公告)号:US10999004B2
公开(公告)日:2021-05-04
申请号:US16529502
申请日:2019-08-01
Inventor: Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
IPC: H04L1/00 , H03M13/11 , H03M13/03 , H03M13/31 , H03M13/00 , H03M13/25 , H03M13/27 , H03M13/29 , H04L27/26
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号:US20210091793A1
公开(公告)日:2021-03-25
申请号:US16849261
申请日:2020-04-15
Applicant: Silicon Motion, Inc.
Inventor: Shiuan-Hao KUO
Abstract: A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.
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7.
公开(公告)号:US10958293B1
公开(公告)日:2021-03-23
申请号:US16806569
申请日:2020-03-02
Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
Inventor: Ronit Bustin
Abstract: A method of near-lossless universal data compression using correlated data sequences includes detecting first target surroundings via a first sensor, encoding a first data sequence indicative of the detected target surroundings, and communicating to an electronic controller, the encoded first data sequence. The method additionally includes detecting the first target surroundings via a second sensor, and encoding a second data sequence indicative of the target surroundings detected by the second sensor. The method also includes communicating the encoded second data sequence to the controller. The method additionally includes decoding, via the controller, the encoded first and second data sequences. The method also includes, via the controller, determining a statistical correlation between the decoded first and second data sequences and formulating a mapping function having reduced cardinality and indicative of the determined statistical correlation. Furthermore, the method includes feeding back the mapping function by the controller to the first processor.
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公开(公告)号:US20200162194A1
公开(公告)日:2020-05-21
申请号:US16524613
申请日:2019-07-29
Applicant: INTEL CORPORATION
Inventor: NAUSHEEN ANSARI , ZIV KABIRY , GAL YEDIDIA
Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.
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公开(公告)号:US10122385B2
公开(公告)日:2018-11-06
申请号:US15505913
申请日:2015-07-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok-Ki Ahn , Woo-Myoung Park , Min Sagong , Chi-Woo Lim , Sung-Nam Hong
Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.
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公开(公告)号:US10091035B2
公开(公告)日:2018-10-02
申请号:US15457935
申请日:2017-03-13
Applicant: KANDOU LABS, S.A.
Inventor: John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.
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