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    TRANSMITTER, RECEIVER, AND TRANSCEIVER INCLUDING TRANSMITTER AND RECEIVER
    1.
    发明公开
    TRANSMITTER, RECEIVER, AND TRANSCEIVER INCLUDING TRANSMITTER AND RECEIVER 审中-公开

    公开(公告)号：US20240305331A1

    公开(公告)日：2024-09-12

    申请号：US18581635

    申请日：2024-02-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyun Jun PARK ,  Woo-Seok CHOI

    IPC分类号： H04B3/32 ,  H04L25/08 ,  H04L25/49

    CPC分类号： H04B3/32 ,  H04L25/085 ,  H04L25/4923

    摘要： A communication system includes a transmitter that encodes binary bits of each of a plurality of data streams into a plurality of symbols and converts the plurality of symbols into a plurality of output signals, respectively corresponding to a plurality of channels, the converting based on a transmission rule defined by a first matrix; and a receiver that combines the plurality of output signals, received through the plurality of channels, the combining based on a reception rule defined by a second matrix, the combining restoring the plurality of symbols, and the receiver decodes the plurality of symbols into the binary bits. The first matrix and the second matrix are determined based on a third matrix that models a crosstalk effect between adjacent channels from among the plurality of channels, to reduce the crosstalk effect.

    USING FULL TERNARY TRANSCODING IN I3C HIGH DATA RATE MODE
    3.
    发明申请
    USING FULL TERNARY TRANSCODING IN I3C HIGH DATA RATE MODE 审中-公开

    公开(公告)号：US20180062887A1

    公开(公告)日：2018-03-01

    申请号：US15659408

    申请日：2017-07-25

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro SENGOKU

    IPC分类号： H04L25/49 ,  H04L7/00

    CPC分类号： H04L25/4923 ,  G06F13/4291 ,  H03M13/09 ,  H04L7/0037 ,  H04L7/0087 ,  H04L25/14 ,  H04L25/4906

    摘要： Apparatus, systems and methods for improving coexistence on a multi-wire interface are disclosed. A method of transmitting data on a multi-wire interface includes providing a plurality of data bits in a word to be transmitted on the multi-wire interface, transcoding the word to be transmitted to obtain a first multi-digit ternary number representative of the numerical value of the word to be transmitted, inserting marker digits into the first multi-digit ternary number to obtain a second multi-digit ternary number, and generating a sequence of symbols. Each symbol in the sequence of symbols may be generated using a digit of the second multi-digit ternary number and a preceding symbol in the sequence of symbols. The preconfigured values and the preconfigured locations of the marker digits may be selected to prevent occurrence of I3C HDR Exit or HDR I3C Restart signaling when the sequence of symbols is transmitted on the multi-wire interface.

    METHOD AND DEVICE FOR TRANSMITTING PAY LOAD SEQUENCE
    7.
    发明申请
    METHOD AND DEVICE FOR TRANSMITTING PAY LOAD SEQUENCE 有权
    用于发送支付负载序列的方法和装置

    公开(公告)号：US20170063579A1

    公开(公告)日：2017-03-02

    申请号：US15033352

    申请日：2014-10-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Chang Soon PARK ,  Young Jun HONG ,  Sujit JOS ,  Young Soo KIM ,  Chandrashekhar Thejaswi PS ,  Kiran BYNAM ,  Manoj CHOUDHARY

    IPC分类号： H04L25/03 ,  H04L27/04 ,  H04B1/709

    CPC分类号： H04L25/03834 ,  H04B1/709 ,  H04L25/03312 ,  H04L25/4923 ,  H04L27/04

    摘要： The present invention relates to a method and a device for transmitting a pay load sequence, and provides in one embodiment a transmitter comprising a first signal converter for converting a ternary payload sequence composed of elements −1, 0, or 1 into a first signal, wherein the first signal converter comprises: a ternary sequence mapper for generating the ternary payload sequence by mapping a pre-designed sequence into a binary data sequence; and a converter for converting the ternary payload sequence into the first signal.

    摘要翻译： 本发明涉及一种用于发送付费负载序列的方法和装置，并且在一个实施例中提供一种发射机，其包括用于将由元素-1,0或1组成的三元有效载荷序列转换为第一信号的第一信号转换器， 其中所述第一信号转换器包括：三进制序列映射器，用于通过将预先设计的序列映射成二进制数据序列来产生所述三进制有效载荷序列; 以及用于将三进制有效载荷序列转换为第一信号的转换器。

    Multiphase clock data recovery circuit calibration
    9.
    发明授权
    Multiphase clock data recovery circuit calibration 有权
    多相时钟数据恢复电路校准

    公开(公告)号：US09485080B1

    公开(公告)日：2016-11-01

    申请号：US14842610

    申请日：2015-09-01

    申请人： QUALCOMM Incorporated

    发明人： Ying Duan ,  Chulkyu Lee ,  Harry Dang ,  Ohjoon Kwon

    IPC分类号： H04L7/00 ,  H04L5/00 ,  H04L7/08

    CPC分类号： H04L7/0008 ,  H03K5/135 ,  H04L5/0048 ,  H04L7/033 ,  H04L7/04 ,  H04L7/08 ,  H04L25/0272 ,  H04L25/4923

    摘要： Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.

    摘要翻译： 公开了用于时钟校准的方法，装置和系统。 一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率 时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有 小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟周期，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。

    Apparatuses and methods for reducing switching jitter
    10.
    发明授权
    Apparatuses and methods for reducing switching jitter 有权
    减少开关抖动的装置和方法

    公开(公告)号：US09473291B2

    公开(公告)日：2016-10-18

    申请号：US14325837

    申请日：2014-07-08

    申请人： Intel Corporation

    发明人： Jonggab Kil

    IPC分类号： H04J3/06 ,  H04L7/00 ,  H04L25/14 ,  H04L25/49

    CPC分类号： H04L7/0041 ,  H04L7/0091 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4923

    摘要： Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.

    摘要翻译： 描述了用于减少信道物理层（C-PHY）切换抖动的装置和方法。 装置可以包括模式相关延迟电路，以检测相应线路上的至少三个数据信号的切换模式，并且基于切换模式自适应地改变至少三个数据信号的延迟。 该装置还可以包括耦合到模式相关延迟电路的发送器，以发送至少三个数据信号。