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    C-PHY data-triggered edge generation with intrinsic half-rate operation
    1.
    发明授权
    C-PHY data-triggered edge generation with intrinsic half-rate operation 有权

    公开(公告)号：US11327914B1

    公开(公告)日：2022-05-10

    申请号：US17162497

    申请日：2021-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Da Ying ,  Shih-Wei Chou ,  Ying Duan ,  Abhay Dixit

    IPC: G06F13/20 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

    C-PHY half-rate wire state encoder and decoder
    2.
    发明授权
    C-PHY half-rate wire state encoder and decoder 有权

    公开(公告)号：US11240077B2

    公开(公告)日：2022-02-01

    申请号：US17070219

    申请日：2020-10-14

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Ying Duan ,  Shih-Wei Chou

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    MIPI D-PHY receiver auto rate detection and high-speed settle time control
    3.
    发明授权
    MIPI D-PHY receiver auto rate detection and high-speed settle time control 有权

    公开(公告)号：US11023409B2

    公开(公告)日：2021-06-01

    申请号：US16591719

    申请日：2019-10-03

    Applicant: QUALCOMM Incorporated

    Inventor： Yasser Ahmed ,  Ying Duan ,  Shih-Wei Chou

    IPC: G06F13/42

    Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.

    Frequency doubler based on phase frequency detectors using rising edge delay
    5.
    发明授权
    Frequency doubler based on phase frequency detectors using rising edge delay 有权

    公开(公告)号：US10944386B1

    公开(公告)日：2021-03-09

    申请号：US16928218

    申请日：2020-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Jing Wu ,  Ying Duan ,  Zhi Zhu

    IPC: H03K5/00 ,  H03K5/135 ,  H03B19/14

    Abstract: Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.

    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING
    6.
    发明申请
    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING 审中-公开

    公开(公告)号：US20180131503A1

    公开(公告)日：2018-05-10

    申请号：US15348290

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

    IPC: H04L7/00 ,  H04L29/06

    CPC classification number: H04L7/0012 ,  G06F13/40 ,  G06F13/4291 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337 ,  H04L25/14 ,  H04L25/49 ,  H04L69/28

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

    C-PHY half-rate wire state encoder and decoder
    8.
    发明授权
    C-PHY half-rate wire state encoder and decoder 有权

    公开(公告)号：US11641294B2

    公开(公告)日：2023-05-02

    申请号：US17589083

    申请日：2022-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Ying Duan ,  Shih-Wei Chou

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
    10.
    发明授权
    Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces 有权

    公开(公告)号：US11038666B1

    公开(公告)日：2021-06-15

    申请号：US16711230

    申请日：2019-12-11

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou

    IPC: H04L7/033 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multiphase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

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