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    Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
    2.
    发明授权
    Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces 有权

    公开(公告)号：US11038666B1

    公开(公告)日：2021-06-15

    申请号：US16711230

    申请日：2019-12-11

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou

    IPC: H04L7/033 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multiphase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING
    4.
    发明申请
    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING 审中-公开

    公开(公告)号：US20180131503A1

    公开(公告)日：2018-05-10

    申请号：US15348290

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

    IPC: H04L7/00 ,  H04L29/06

    CPC classification number: H04L7/0012 ,  G06F13/40 ,  G06F13/4291 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337 ,  H04L25/14 ,  H04L25/49 ,  H04L69/28

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

    C-PHY data-triggered edge generation with intrinsic half-rate operation
    6.
    发明授权
    C-PHY data-triggered edge generation with intrinsic half-rate operation 有权

    公开(公告)号：US11327914B1

    公开(公告)日：2022-05-10

    申请号：US17162497

    申请日：2021-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Da Ying ,  Shih-Wei Chou ,  Ying Duan ,  Abhay Dixit

    IPC: G06F13/20 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

    Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
    8.
    发明授权
    Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface 有权

    公开(公告)号：US10333690B1

    公开(公告)日：2019-06-25

    申请号：US15971016

    申请日：2018-05-04

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou ,  Chulkyu Lee

    IPC: H04L7/033 ,  H04L7/00 ,  G09G5/00 ,  H04L25/49

    Abstract: Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

    C-PHY half-rate clock and data recovery adaptive edge tracking
    9.
    发明授权
    C-PHY half-rate clock and data recovery adaptive edge tracking 有权

    公开(公告)号：US10033519B2

    公开(公告)日：2018-07-24

    申请号：US15348290

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

    IPC: H04L29/06 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

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