公开(公告)号：US20180109247A1

公开(公告)日：2018-04-19

申请号：US15721750

申请日：2017-09-30

申请人： Realtek Semiconductor Corp.

发明人： FANGJIE YANG ,  Chuan-Ping Tu

IPC分类号： H03K5/135 ,  H04L27/01 ,  H04L7/00 ,  H04L7/033

CPC分类号： H03K5/135 ,  H03K2005/00052 ,  H03K2005/00065 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0337 ,  H04L27/01

摘要： A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.

公开(公告)号：US20160352506A1

公开(公告)日：2016-12-01

申请号：US14983830

申请日：2015-12-30

申请人： Silicon Laboratories Inc.

发明人： Yunteng Huang

IPC分类号： H04L7/033 ,  H03L7/093 ,  H03L7/091 ,  H04L27/227 ,  H04J3/06

CPC分类号： H04L7/0332 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0994 ,  H04J3/0661 ,  H04L7/002 ,  H04L27/2272

摘要： A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

摘要翻译： 更具成本效益的漂移抖动滤波器利用偏移检测器，其接收第一信号和第二信号之间的定时差，并且如果定时差的大小高于预定阈值则提供第一调整量，否则提供第二调整量 零。 求和电路将定时差的大小调整第一或第二调整量。 环路滤波器接收求和电路输出并控制振荡器。 偏移检测器输出（根据定时差的幅度的第一调整值或零）被低通滤波，低通滤波被重新引入振荡器输出或反馈回路。 偏移检测器输出被累加并用于调整来自振荡器的反馈信号的相位。

公开(公告)号：US08831157B1

公开(公告)日：2014-09-09

申请号：US14040203

申请日：2013-09-27

申请人： Altera Corporation

发明人： Lip Kai Soh

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331

摘要： One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种基于插值器的时钟和数据恢复电路，其包括解复用器和投票电路。 解复用器被布置为对来自采样器的反馈信号进行解复用，并且投票电路被布置为对去多路复用的反馈信号进行抽取。 抽取的反馈信号可以被提供给数字滤波器。 另一实施例涉及一种用于从数据信号进行时钟和数据恢复的方法。 该方法包括解复用和抽取反馈信号。 还公开了其它实施例和特征。

公开(公告)号：US08502586B1

公开(公告)日：2013-08-06

申请号：US13287109

申请日：2011-11-01

申请人： Eric Naviasky ,  Thomas E. Wilson

发明人： Eric Naviasky ,  Thomas E. Wilson

IPC分类号： H03H11/16 ,  H03K5/13

CPC分类号： H03K5/135 ,  H03K2005/00052 ,  H04L7/002 ,  H04L7/0337

摘要： In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

摘要翻译： 在本发明的一个实施例中，公开了一种用于产生具有所选相位的时钟输出信号的方法。 该方法包括选择时钟输出信号的相位延迟; 在第一相位输入时钟期间用第一加权电流对电容器充电，在第二相输入时钟的一部分期间用第二加权电流对电容器充电，以及确定电容器两端的电压是否大于或等于阈值电压 以产生具有所选相位延迟的时钟输出信号的第一边沿。 第一加权电流可以具有对M的加权，以响应于所选择的相位延迟以预定的电压变化率对电容器充电。 第二加权电流可以具有M的M的加权，以恒定的变化率对电容器充电。

公开(公告)号：US20130187688A1

公开(公告)日：2013-07-25

申请号：US13612770

申请日：2012-09-12

申请人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

发明人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

IPC分类号： H03L7/08

CPC分类号： H03C5/00 ,  H04L7/002 ,  H04L7/0331

摘要： A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

摘要翻译： 用于产生频率调制时钟的频率调制路径包括直接调制振荡器频率的直接馈送输入和用于补偿频率调制对相位误差的影响的补偿馈入输入; 其中所述补偿馈送输入由作为所述振荡器的整数边缘除法的下分频时钟再采样。 用于产生参考相位输出的参考相位发生器包括重采样电路，累加器和采样器。 重采样电路用于对调制频率指令字（FCW）进行重采样以产生多个采样。 累加器用于累积样本以产生累积结果。 采样器用于根据频率参考时钟对累积结果进行采样，并且因此产生采样结果，其中至少根据采样结果来更新参考相位输出。

公开(公告)号：US08433022B2

公开(公告)日：2013-04-30

申请号：US13113461

申请日：2011-05-23

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/002 ,  H04L7/041

摘要： A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

摘要翻译： 时钟数据恢复电路包括：基于采样时钟接收输入数据的接收电路;将从接收电路输出的串行数据转换成并行数据的解复用器;时钟/数据恢复部件，其从并行数据输出端检测相位信息; 并且通过基于相位信息调整参考时钟的相位来生成采样时钟，执行从解复用器输出的并行数据的频率分析的数据模式分析器和检测时钟恢复状态的混叠检测器 基于并行数据频率的分析结果。

公开(公告)号：US08415996B1

公开(公告)日：2013-04-09

申请号：US13167956

申请日：2011-06-24

申请人： Wai Tat Wong

发明人： Wai Tat Wong

IPC分类号： H03L7/00

CPC分类号： H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/002 ,  H04L7/0337

摘要： Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.

摘要翻译： 提出了用于校正时钟信号相位的方法，电路和装置。 在一种方法中，包括用于从多个输入行接收具有相应输入时钟相位的多个输入时钟信号的操作。 输入时钟相位形成有序序列的时钟相位。 该方法还包括用于在多个输出线路上以相应的输出时钟相位发送多个输出时钟信号的操作。 输入和输出线耦合到串联的电阻环，其中环中的每个电阻器具有耦合到输入线的端子，而耦合到输出线的另一端子。 此外，每个输出时钟相位具有在时钟相位的有序序列的连续输入时钟相位之间的值。

公开(公告)号：US20120039426A1

公开(公告)日：2012-02-16

申请号：US13113461

申请日：2011-05-23

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/002 ,  H04L7/041

摘要： A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

摘要翻译： 时钟数据恢复电路包括：基于采样时钟接收输入数据的接收电路;将从接收电路输出的串行数据转换成并行数据的解复用器;时钟/数据恢复部件，其从并行数据输出端检测相位信息; 并且通过基于相位信息调整参考时钟的相位来生成采样时钟，执行从解复用器输出的并行数据的频率分析的数据模式分析器和检测时钟恢复状态的混叠检测器 基于并行数据频率的分析结果。

公开(公告)号：US20100318860A1

公开(公告)日：2010-12-16

申请号：US12793039

申请日：2010-06-03

申请人： Seiji Ohbi

发明人： Seiji Ohbi

IPC分类号： G06F11/07

CPC分类号： H04L7/002 ,  H04L67/42 ,  H04N5/765 ,  H04N21/234318 ,  H04N21/4302 ,  H04N21/4307 ,  H04N21/43615

摘要： An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

摘要翻译： 提供了一种信息处理装置，其包括：发送单元，用于发送用于查询另一设备的查询请求，以获得由其他设备保存的计数值;接收单元，用于从该另一设备接收计数值的返回;校正单元， 基于所接收的计数值，在预定的时间段执行用于使采样频率与这种其他设备同步的校正处理，以及用于基于采样频率与这种其他设备同步再现内容的再现单元。 校正单元通过考虑在查询请求的发送和返回的接收之间的往返时间以及在先前校正时间发生的残差而进行校正。

公开(公告)号：US20090154626A1

公开(公告)日：2009-06-18

申请号：US11957451

申请日：2007-12-15

申请人： Warren R. Anderson ,  Matthew E. Becker

发明人： Warren R. Anderson ,  Matthew E. Becker

IPC分类号： H04L7/02

CPC分类号： H04L7/0337 ,  H04L7/002 ,  H04L7/0058

摘要： The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe system performance degradation penalty that may occur from data traffic stoppage during the retraining events. The available bandwidth is further increased by removing a timing error which results in increasing a timing margin for other components. This results in an increase in the maximum speed of systems with high speed I/O and communication transceiver Integrated Circuits (IC)s.

摘要翻译： 输入/输出（I / O）通信链路的可用带宽通过消除对通信链路上的再训练事件的需要而增加。 这导致在再培训事件期间，可能会从数据流量停止中消除潜在的严重的系统性能降级损失。 通过消除导致增加其他组件的定时裕度的定时错误，进一步增加了可用带宽。 这导致具有高速I / O和通信收发器集成电路（IC）的系统的最大速度的增加。