公开(公告)号：US07409002B2

公开(公告)日：2008-08-05

申请号：US10676565

申请日：2003-09-30

申请人： Matthew E. Becker ,  Karl Wyatt

发明人： Matthew E. Becker ,  Karl Wyatt

IPC分类号： H03C5/00

CPC分类号： H04L25/4917 ,  H04J7/00 ,  H04L25/493

摘要： According to an embodiment of the invention, a method and apparatus for signal modulation are described. According to an embodiment of the invention, a method comprises producing and transferring a modulated signal. The modulation of the signal is over a plurality of amplitude levels, including at least a first amplitude level, a second amplitude level and a third amplitude level, and over a plurality of time slots, including at least a first time slot, a second time slot, and a third time slot. The modulated signal transitions from the first amplitude level to the second amplitude level in the first phase slot, remains at the second amplitude level in the second time slot, and transitions from the second amplitude level to the third amplitude level in a third time slot.

摘要翻译： 根据本发明的实施例，描述了用于信号调制的方法和装置。 根据本发明的实施例，一种方法包括产生和传送调制信号。 信号的调制在多个幅度水平上，包括至少第一幅度电平，第二幅度电平和第三幅度电平以及多个时隙，包括至少第一时隙，第二时间 插槽和第三个时隙。 调制信号从第一相位时隙中的第一幅度电平转换到第二幅度电平在第二时隙中保持在第二幅度电平，并且在第三时隙中从第二幅度电平转变到第三幅度电平。

公开(公告)号：US06754685B2

公开(公告)日：2004-06-22

申请号：US09745759

申请日：2000-12-21

申请人： Matthew E. Becker

发明人： Matthew E. Becker

IPC分类号： G06F700

CPC分类号： G06F5/015 ,  G06F7/607 ,  G06F2207/3872

摘要： A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

摘要翻译： 已经开发了一种将人口计数操作与位移操作相结合的方法。 该方法可用于通过稀疏向量的总体计数来增加指针。 该方法进一步提供平衡在群体计数和比特移位电路的输入处的输入负载，使得操作的执行更平衡，其实际上提高了计算速度和效率。 还开发了一种集成人口计数电路和位移电路的装置。 该装置包括多个动态阶段，随后是静止阶段。 动态阶段涉及动态节点的使用，这些动态节点表示取决于指针中各个比特的值和稀疏向量的值。 该装置还允许通过电路重复的扩展，使得装置的拓扑可以根据指针的大小和稀疏矢量而改变。

公开(公告)号：US20090154626A1

公开(公告)日：2009-06-18

申请号：US11957451

申请日：2007-12-15

申请人： Warren R. Anderson ,  Matthew E. Becker

发明人： Warren R. Anderson ,  Matthew E. Becker

IPC分类号： H04L7/02

CPC分类号： H04L7/0337 ,  H04L7/002 ,  H04L7/0058

摘要： The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe system performance degradation penalty that may occur from data traffic stoppage during the retraining events. The available bandwidth is further increased by removing a timing error which results in increasing a timing margin for other components. This results in an increase in the maximum speed of systems with high speed I/O and communication transceiver Integrated Circuits (IC)s.

摘要翻译： 输入/输出（I / O）通信链路的可用带宽通过消除对通信链路上的再训练事件的需要而增加。 这导致在再培训事件期间，可能会从数据流量停止中消除潜在的严重的系统性能降级损失。 通过消除导致增加其他组件的定时裕度的定时错误，进一步增加了可用带宽。 这导致具有高速I / O和通信收发器集成电路（IC）的系统的最大速度的增加。

公开(公告)号：US06799308B2

公开(公告)日：2004-09-28

申请号：US10325806

申请日：2002-12-19

申请人： Eileen H. You ,  Matthew E. Becker ,  Thomas E. Dillinger ,  Micah C. Knapp ,  Daniel J. Flees ,  Peter R. O'Brien ,  Chung Lau Chan

发明人： Eileen H. You ,  Matthew E. Becker ,  Thomas E. Dillinger ,  Micah C. Knapp ,  Daniel J. Flees ,  Peter R. O'Brien ,  Chung Lau Chan

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

公开(公告)号：US06794902B2

公开(公告)日：2004-09-21

申请号：US10172574

申请日：2002-06-14

申请人： Matthew E. Becker ,  Harry R. Fair, III ,  Marc E. Lamere ,  Jonathan A. White

发明人： Matthew E. Becker ,  Harry R. Fair, III ,  Marc E. Lamere ,  Jonathan A. White

IPC分类号： H03K19096

CPC分类号： H03K19/0016 ,  H03K19/01728

摘要： Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

摘要翻译： 描述了用于改进逻辑电路的方法和系统。 通过使用用于将电源连接到虚拟接地的电压减小器，降压器在时钟的一个相位期间将由电源供给的电压降低到虚拟接地，从而提高逻辑电路的速度和效率。