- 专利标题: PHASE INTERPOLATOR AND CLOCK GENERATING METHOD
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申请号: US15721750申请日: 2017-09-30
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公开(公告)号: US20180109247A1公开(公告)日: 2018-04-19
- 发明人: FANGJIE YANG , Chuan-Ping Tu
- 申请人: Realtek Semiconductor Corp.
- 优先权: CN201610897942.3 20161014
- 主分类号: H03K5/135
- IPC分类号: H03K5/135 ; H04L27/01 ; H04L7/00 ; H04L7/033
摘要:
A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.
公开/授权文献
- US10205443B2 Phase interpolator and clock generating method 公开/授权日:2019-02-12
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