公开(公告)号：US08415996B1

公开(公告)日：2013-04-09

申请号：US13167956

申请日：2011-06-24

申请人： Wai Tat Wong

发明人： Wai Tat Wong

IPC分类号： H03L7/00

CPC分类号： H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/002 ,  H04L7/0337

摘要： Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.

摘要翻译： 提出了用于校正时钟信号相位的方法，电路和装置。 在一种方法中，包括用于从多个输入行接收具有相应输入时钟相位的多个输入时钟信号的操作。 输入时钟相位形成有序序列的时钟相位。 该方法还包括用于在多个输出线路上以相应的输出时钟相位发送多个输出时钟信号的操作。 输入和输出线耦合到串联的电阻环，其中环中的每个电阻器具有耦合到输入线的端子，而耦合到输出线的另一端子。 此外，每个输出时钟相位具有在时钟相位的有序序列的连续输入时钟相位之间的值。