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    Apparatus and methods for high-speed interpolator-based clock and data recovery
    1.
    发明授权
    Apparatus and methods for high-speed interpolator-based clock and data recovery 有权
    用于基于高速内插器的时钟和数据恢复的装置和方法

    公开(公告)号：US08831157B1

    公开(公告)日：2014-09-09

    申请号：US14040203

    申请日：2013-09-27

    申请人： Altera Corporation

    发明人： Lip Kai Soh

    IPC分类号： H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331

    摘要： One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种基于插值器的时钟和数据恢复电路，其包括解复用器和投票电路。 解复用器被布置为对来自采样器的反馈信号进行解复用，并且投票电路被布置为对去多路复用的反馈信号进行抽取。 抽取的反馈信号可以被提供给数字滤波器。 另一实施例涉及一种用于从数据信号进行时钟和数据恢复的方法。 该方法包括解复用和抽取反馈信号。 还公开了其它实施例和特征。

    Priority control phase shifts for clock signals
    2.
    发明授权
    Priority control phase shifts for clock signals 有权
    时钟信号的优先级控制相移

    公开(公告)号：US09059720B1

    公开(公告)日：2015-06-16

    申请号：US14169680

    申请日：2014-01-31

    申请人： Altera Corporation

    发明人： Lip Kai Soh

    IPC分类号： H03L7/091

    CPC分类号： H03L7/091 ,  H04L7/033

    摘要： A circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

    摘要翻译： 电路包括采样器电路，滤波器电路，控制电路和相移电路。 采样器电路响应于时钟信号采样输入数据。 滤波器电路耦合到采样器电路。 控制电路耦合到滤波电路。 相移电路向采样电路提供时钟信号。 控制电路使得相移电路将时钟信号的相位移位第一相移，并且在时钟信号的相位偏移第一相移之后，响应于滤波器电路指示 以使时钟信号的相位偏移大于预定义的相移。