公开(公告)号：US08683401B2

公开(公告)日：2014-03-25

申请号：US13177096

申请日：2011-07-06

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals.

摘要翻译： 信息处理装置包括：物理属性值生成单元，生成用于改变包含多个电路元件的目标路径在预定的波动范围内的信号传播时间的多个物理属性值;元件延迟计算单元，用于计算延迟时间 根据所生成的物理属性值中的每一个通过电路元件的每个信号和传播时间计算单元，基于信号的延迟时间来计算目标路径的信号传播时间。

公开(公告)号：US08504332B2

公开(公告)日：2013-08-06

申请号：US12792979

申请日：2010-06-03

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance value.

摘要翻译： 非瞬时计算机可读记录介质中存储有使处理器执行输入集中常数电容值中包含的驱动能力值，集总常数电容值和输入电容值的程序，分别定义在 电路模型，并且基于驱动能力值和集总常数电容值进一步输入电路模型的第一延迟时间; 设置电路模型，驱动能力值，集总常数电容值和输入电容值; 通过向仿真器提供其中设置的值的电路模型，获取电路模型的第二延迟时间; 计算第一延迟时间和第二延迟时间的相对评估值; 将存储装置和延迟时间校正系数存储到与驱动能力值，集总常数电容值和输入电容值相关的相对评价值。

公开(公告)号：US20100218153A1

公开(公告)日：2010-08-26

申请号：US12640677

申请日：2009-12-17

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path, calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path, and calculating a source propagation delay time of the source path by merging the propagation delay time of each of the partitioned paths.

摘要翻译： 一种设计支持方法，包括基于给定条件将电路信息的分割路径划分为分割路径，基于对应的分割路径中包含的单元的延迟的变化值，计算每个分割路径的变化值， 基于对应的分割路径的变化值，分割出各分割路径的分割传播延迟时间，并且通过合并每个分割路径的传播延迟时间来计算源路径的源传播延迟时间。

公开(公告)号：US07243283B2

公开(公告)日：2007-07-10

申请号：US11095662

申请日：2005-04-01

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G01R31/28

CPC分类号： G01R31/31703

摘要： A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are input as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is input to each digital filter from a built-in self test (BIST) controller, abnormal circuits can be detected based on comparison results of the comparison circuits.

摘要翻译： 一种具有相同配置的多个电路的半导体器件，其中由于不需要与电路数量相对应的数量的期望值，因此在短时间内有效地执行操作测试。 该半导体器件具有相同配置的第一，第二和第三数字滤波器。 为了测试这些数字滤波器，每个数字滤波器分别提供比较输出值和期望值的比较电路。 数字滤波器和比较电路被菊花链式连接，使得第一和第二数字滤波器的输出值分别作为与第二和第三数字滤波器对应的比较电路的期望值输入。 当从内置自检（BIST）控制器向每个数字滤波器输入相同的测试信号时，可以根据比较电路的比较结果检测异常电路。

公开(公告)号：US08713500B2

公开(公告)日：2014-04-29

申请号：US12552015

申请日：2009-09-01

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G06F17/50 ,  G01R29/02 ,  G01R19/00 ,  H03L5/00

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.

摘要翻译： 计算机执行信号延迟评估程序，以确定用于定义第一电路块的转换速率的参考电平是否不同于用于接收来自第一电路块的输出信号的第二电路块的参考电平。 基于在第一和第二电路块之间找到的参考电平的差异，计算机将从第一电路块提供的输出信号的输出转换速率校正到第二电路块。

公开(公告)号：US08381146B2

公开(公告)日：2013-02-19

申请号：US13049595

申请日：2011-03-16

申请人： Mitsuru Onodera

发明人： Mitsuru Onodera

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

摘要翻译： 计算机可读的非暂时介质中存储有设计支持程序，该程序支持程序使得能够访问存储在每个单元中的存储设备的计算机，该单元的输出电压值是从开始变化的每个经过时间段 施加到单元的输入电压，以执行处理。 该处理包括：从设计中的电路的电路信息中选择与设计的单元有关的每个经过时间段的输出电压值，从存储设备中提取; 基于特定电压值确定要被校正的提取的经过时间段; 将设计中的单元的输出的时间常数添加到确定为校正的经过时间段; 并且输出用于每个经修正的经过时间段的输出电压值和对于未确定用于校正的每个经过时间段的输出电压值。

公开(公告)号：US20110314434A1

公开(公告)日：2011-12-22

申请号：US13049674

申请日：2011-03-16

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

公开(公告)号：US20110314433A1

公开(公告)日：2011-12-22

申请号：US13049595

申请日：2011-03-16

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

摘要翻译： 计算机可读的非暂时介质中存储有设计支持程序，该程序支持程序使得能够访问存储在每个单元中的存储设备的计算机，该单元的输出电压值是从开始变化的每个经过时间段 施加到单元的输入电压，以执行处理。 该处理包括：从设计中的电路的电路信息中选择与设计的单元有关的每个经过时间段的输出电压值，从存储设备中提取; 基于特定电压值确定要被校正的提取的经过时间段; 将设计中的单元的输出的时间常数添加到确定为校正的经过时间段; 并且输出用于每个经修正的经过时间段的输出电压值和对于未确定用于校正的每个经过时间段的输出电压值。

公开(公告)号：US20120036490A1

公开(公告)日：2012-02-09

申请号：US13177096

申请日：2011-07-06

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals.

摘要翻译： 信息处理装置包括：物理属性值生成单元，生成用于改变包含多个电路元件的目标路径在预定的波动范围内的信号传播时间的多个物理属性值;元件延迟计算单元，用于计算延迟时间 根据所生成的物理属性值中的每一个通过电路元件的每个信号和传播时间计算单元，基于信号的延迟时间来计算目标路径的信号传播时间。

公开(公告)号：US20090319972A1

公开(公告)日：2009-12-24

申请号：US12552015

申请日：2009-09-01

申请人： Mitsuru ONODERA

发明人： Mitsuru ONODERA

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.

摘要翻译： 计算机执行信号延迟评估程序，以确定用于定义第一电路块的转换速率的参考电平是否不同于用于接收来自第一电路块的输出信号的第二电路块的参考电平。 基于在第一和第二电路块之间找到的参考电平的差异，计算机将从第一电路块提供的输出信号的输出转换速率校正到第二电路块。