公开(公告)号：US11327914B1

公开(公告)日：2022-05-10

申请号：US17162497

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Da Ying ,  Shih-Wei Chou ,  Ying Duan ,  Abhay Dixit

IPC: G06F13/20 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.