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    Multiphase clock data recovery for a 3-phase interface
    4.
    发明授权
    Multiphase clock data recovery for a 3-phase interface 有权
    三相接口的多相时钟数据恢复

    公开(公告)号：US09496879B1

    公开(公告)日：2016-11-15

    申请号：US14842644

    申请日：2015-09-01

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Chulkyu Lee ,  Shih-Wei Chou ,  Harry Dang ,  Ohjoon Kwon

    IPC: H03D3/24 ,  H03L7/08 ,  H03L7/081 ,  H04L7/00 ,  H04L7/033

    CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H04L7/0037 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/04 ,  H04L25/4917

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.

    Abstract translation: 公开了通过多线，多相接口进行数据通信的方法，装置和系统。 一种数据通信方法包括配置时钟恢复电路以提供第一时钟信号，该第一时钟信号包括在接口上发送的每个符号的脉冲，其中符号以第一频率在接口上发送，调整时钟恢复电路的环路延迟 修改第一时钟以具有不超过第一频率的一半的第二频率，其中时钟恢复电路在第一时钟信号中产生用于整数符号中的第一个的脉冲，并且抑制其他符号的脉冲产生 整数个符号，配置时钟发生电路以提供第二时钟信号，以及使用第一时钟信号和第二时钟信号从接口捕获符号。

    Multiphase clock data recovery circuit calibration
    5.
    发明授权
    Multiphase clock data recovery circuit calibration 有权
    多相时钟数据恢复电路校准

    公开(公告)号：US09485080B1

    公开(公告)日：2016-11-01

    申请号：US14842610

    申请日：2015-09-01

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Chulkyu Lee ,  Harry Dang ,  Ohjoon Kwon

    IPC: H04L7/00 ,  H04L5/00 ,  H04L7/08

    CPC classification number: H04L7/0008 ,  H03K5/135 ,  H04L5/0048 ,  H04L7/033 ,  H04L7/04 ,  H04L7/08 ,  H04L25/0272 ,  H04L25/4923

    Abstract: Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.

    Abstract translation: 公开了用于时钟校准的方法，装置和系统。 一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率 时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有 小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟周期，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。

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