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公开(公告)号：US20220082648A1
公开(公告)日：2022-03-17
申请号：US17445342
申请日：2021-08-18
申请人： NXP USA, Inc.
摘要： There is described a method of verifying a function of a power supply monitor in a digital control system, wherein the power supply monitor is adapted to monitor whether or not a power supply voltage is between a lower threshold value and an upper threshold value. The method comprises: setting the power supply voltage to a first value, the first value being below the lower threshold value, checking, as a first check, that the power supply monitor indicates that the power supply voltage is below the lower threshold value, setting the power supply voltage to a second value, the second value being above the lower threshold value and below the upper threshold value, checking, as a second check, that the power supply monitor indicates that the power supply voltage is above the lower threshold value, and verifying the function of the power supply monitor if both the first check and the second check are successful. There is also described a corresponding device and computer program.
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公开(公告)号：US20240080035A1
公开(公告)日：2024-03-07
申请号：US18455291
申请日：2023-08-24
申请人： NXP USA, INC.
发明人： Thierry Dominique Yves Cassagnes , Francesco d'Esposito , Pascal Sandrez , Olivier Tico , Simon Brule
摘要： A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.
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公开(公告)号：US20180121282A1
公开(公告)日：2018-05-03
申请号：US15705332
申请日：2017-09-15
申请人： NXP USA, Inc.
发明人： Andres Barrilado Gonzalez , Ralf Reuter , Dominique Delbecq , Francesco d'Esposito , Arnaud Sion , Gustavo Adolfo Guarin Aristizabal , Marcel Christoph Welpot
CPC分类号： G06F11/1004 , G06F3/0619 , G06F3/064 , G06F3/0683 , G06F11/08 , G06F11/10
摘要： A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.
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