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公开(公告)号：US10545895B1
公开(公告)日：2020-01-28
申请号：US15876473
申请日：2018-01-22
IPC分类号： G06F13/28
摘要： Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.
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公开(公告)号：US11481148B1
公开(公告)日：2022-10-25
申请号：US17362352
申请日：2021-06-29
IPC分类号： G06F3/06 , H03K17/0412
摘要： This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.
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公开(公告)号：US09754646B1
公开(公告)日：2017-09-05
申请号：US15342974
申请日：2016-11-03
CPC分类号： G11C7/1012 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093
摘要： Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.
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公开(公告)号：US11545968B1
公开(公告)日：2023-01-03
申请号：US16877123
申请日：2020-05-18
发明人： Moo Sung Chae , Thomas Evan Wilson
IPC分类号： H03K5/1252 , G11C5/14 , H03H7/06 , H03F3/45
摘要： Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.
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公开(公告)号：US10705984B1
公开(公告)日：2020-07-07
申请号：US16143123
申请日：2018-09-26
摘要： Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).
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公开(公告)号：US09767888B1
公开(公告)日：2017-09-19
申请号：US15396046
申请日：2016-12-30
IPC分类号： G11C5/06 , G11C11/4094 , G11C11/4091 , G11C11/4074 , H03F3/45 , H03K17/687
CPC分类号： H03K17/6872 , G11C11/4074 , G11C11/4093 , G11C29/022 , G11C29/023 , G11C29/028 , H03F3/3022 , H03F3/45179 , H03F2203/30006 , H03F2203/45344
摘要： Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
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公开(公告)号：US11677593B1
公开(公告)日：2023-06-13
申请号：US17752829
申请日：2022-05-24
发明人： Vinod Kumar , Thomas Evan Wilson
IPC分类号： H04L25/03
CPC分类号： H04L25/03057
摘要： Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.
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公开(公告)号：US10389368B1
公开(公告)日：2019-08-20
申请号：US15943491
申请日：2018-04-02
摘要： Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.
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公开(公告)号：US10193555B1
公开(公告)日：2019-01-29
申请号：US15197324
申请日：2016-06-29
IPC分类号： G06F17/50 , H03K19/0948 , G11C14/00 , H03F1/30 , G11C11/412 , H03K17/687
摘要： Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
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10.发明授权Methods and devices for a DDR memory driver using a voltage translation capacitor 有权使用电压转换电容器的DDR存储器驱动器的方法和器件公开(公告)号：US09589627B1
公开(公告)日：2017-03-07
申请号：US15169508
申请日：2016-05-31
IPC分类号： G11C7/00 , G11C11/4074 , G11C11/4076 , G11C11/409 , H03K19/003 , H03K17/14
CPC分类号： G11C11/4074 , G11C5/145 , G11C7/1057 , G11C11/4096 , H03K17/145 , H03K19/00315
摘要： Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
摘要翻译： 实施例涉及使用电压转换电容器来设计和创建存储器驱动器电路的系统，方法和计算机可读介质。 一个实施例是包括多个场效应晶体管（FET），互补金属氧化物半导体（CMOS）逻辑门以驱动FET的高速电平转换存储器驱动器装置，以及连接有电压转换电容器的第一端的电压转换电容器 连接到第一P型FET的栅极端子的第二CMOS逻辑门极和电压转换电容器的第二端子的输出。 还描述了包括其他电路，相关方法和包括与生成电路设计文件相关联的指令的媒体的附加实施例。
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