公开(公告)号：US06952377B2

公开(公告)日：2005-10-04

申请号：US10824784

申请日：2004-04-15

申请人： In-young Chung

发明人： In-young Chung

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2207/229

摘要： Provided are a method of writing data into a memory cell with a boosted write voltage and a memory device that performs the method. The method involves (a) transmitting data input in response to a write command to a bitline; (b) writing the input data on the bitline into a memory cell capacitor via a memory cell transistor; (c) generating a write boosting signal in response to the write command and a bitline precharge signal; (d) boosting a voltage of a capacitor connected between the write boosting signal and the bitline in response to the write boosting signal; (e) boosting a voltage of the bitline to a predetermined level; and (f) rewriting the input data into the memory cell capacitor with the boosted voltage of the bitline.

摘要翻译： 提供了一种将数据写入具有升压写电压的存储单元和执行该方法的存储器件的方法。 该方法包括（a）响应写入命令将数据输入发送到位线; （b）经由存储单元晶体管将位线上的输入数据写入存储单元电容器; （c）响应写入命令和位线预充电信号产生写升压信号; （d）响应于写升压信号，升压连接在写升压信号和位线之间的电容器的电压; （e）将所述位线的电压升高到预定水平; 和（f）用位线的升压电压将输入数据改写成存储单元电容器。

公开(公告)号：US20050105344A1

公开(公告)日：2005-05-19

申请号：US10824784

申请日：2004-04-15

申请人： In-young Chung

发明人： In-young Chung

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2207/229

摘要： Provided are a method of writing data into a memory cell with a boosted write voltage and a memory device that performs the method. The method involves (a) transmitting data input in response to a write command to a bitline; (b) writing the input data on the bitline into a memory cell capacitor via a memory cell transistor; (c) generating a write boosting signal in response to the write command and a bitline precharge signal; (d) boosting a voltage of a capacitor connected between the write boosting signal and the bitline in response to the write boosting signal; (e) boosting a voltage of the bitline to a predetermined level; and (f) rewriting the input data into the memory cell capacitor with the boosted voltage of the bitline.

公开(公告)号：US07164295B2

公开(公告)日：2007-01-16

申请号：US10848034

申请日：2004-05-18

申请人： In-young Chung

发明人： In-young Chung

IPC分类号： H03K5/153

CPC分类号： H03K5/1252

摘要： A feedback control system and method thereof are provided. The feedback control method includes (a) comparing the level of a reference signal with the levels of first and second signals, (b) if the levels of the first and second signals are lower than the level of the reference signal, generating a first control signal, if the levels of the first and second signals are higher than the level of the reference signal, generating a second control signal, and if the level of the reference signal is between the level of the first signal and the level of the second signal, generating a third control signal, (c) controlling the level of an output signal in response to the first through third control signals, and (d) outputting the controlled output signal and generating the first signal and the second signal.

摘要翻译： 提供了一种反馈控制系统及其方法。 反馈控制方法包括：（a）将参考信号的电平与第一和第二信号的电平进行比较，（b）如果第一和第二信号的电平低于参考信号的电平，则产生第一控制 信号，如果第一和第二信号的电平高于参考信号的电平，则产生第二控制信号，并且如果参考信号的电平在第一信号的电平和第二信号的电平之间 产生第三控制信号，（c）响应于第一至第三控制信号控制输出信号的电平，以及（d）输出受控输出信号并产生第一信号和第二信号。

公开(公告)号：US20050007146A1

公开(公告)日：2005-01-13

申请号：US10888010

申请日：2004-07-12

申请人： In-young Chung

发明人： In-young Chung

IPC分类号： H01L27/04 ,  G11C7/10 ,  H01L21/822 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003

CPC分类号： H03K19/00361

摘要： An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first node, and a gate to which data is applied. The second transistor may have a first terminal connected to the first node and a second terminal connected to an output node. The noise-eliminating portion may be connected between the gate of the first transistor and a gate of the second transistor. The noise-eliminating portion may be a capacitor. The capacitor may substantially eliminate coupling noise introduced at the gate of the second transistor, due to coupling capacitance between the gate of the second transistor and the output node and coupling capacitance between the gate of the second transistor and the first node, by using the data applied to the gate of the first transistor.

摘要翻译： 输出驱动器可以减少耦合噪声。 输出驱动器可以包括第一晶体管，第二晶体管和/或噪声消除部分。 第一晶体管可以具有连接到第一电压的第一端子，连接到第一节点的第二端子和施加数据的栅极。 第二晶体管可以具有连接到第一节点的第一端子和连接到输出节点的第二端子。 噪声消除部分可以连接在第一晶体管的栅极和第二晶体管的栅极之间。 噪声消除部分可以是电容器。 由于第二晶体管的栅极和输出节点之间的耦合电容以及第二晶体管的栅极与第一节点之间的耦合电容，电容器可以基本上消除在第二晶体管的栅极处引入的耦合噪声， 施加到第一晶体管的栅极。

公开(公告)号：US07248091B2

公开(公告)日：2007-07-24

申请号：US11324951

申请日：2006-01-04

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03H11/26

CPC分类号： H03L7/0812

摘要： A semiconductor device having a delay drift compensation circuit that compensates for a delay drift caused by temperature and voltage variations in a clock tree includes a clock driver having an output port, a first circuit having an input port, a first signal path between the output port of the clock driver and the input port of the first circuit and a first delay drift compensation circuit. The first delay drift compensation circuit, which is coupled with the first signal path, reduces a delay time of the first signal path when a power supply voltage increases, and increases the delay time of the first signal path when a temperature increases.

摘要翻译： 具有补偿由时钟树中的温度和电压变化引起的延迟漂移的延迟漂移补偿电路的半导体器件包括具有输出端口的时钟驱动器，具有输入端口的第一电路，输出端口之间的第一信号路径 的时钟驱动器和第一电路的输入端口以及第一延迟漂移补偿电路。 与第一信号路径耦合的第一延迟漂移补偿电路在电源电压增加时减小第一信号路径的延迟时间，并且当温度升高时增加第一信号路径的延迟时间。

公开(公告)号：US07088125B2

公开(公告)日：2006-08-08

申请号：US10888010

申请日：2004-07-12

申请人： In-young Chung

发明人： In-young Chung

IPC分类号： H03K19/003

CPC分类号： H03K19/00361

摘要： An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first node, and a gate to which data is applied. The second transistor may have a first terminal connected to the first node and a second terminal connected to an output node. The noise-eliminating portion may be connected between the gate of the first transistor and a gate of the second transistor. The noise-eliminating portion may be a capacitor. The capacitor may substantially eliminate coupling noise introduced at the gate of the second transistor, due to coupling capacitance between the gate of the second transistor and the output node and coupling capacitance between the gate of the second transistor and the first node, by using the data applied to the gate of the first transistor.

摘要翻译： 输出驱动器可以减少耦合噪声。 输出驱动器可以包括第一晶体管，第二晶体管和/或噪声消除部分。 第一晶体管可以具有连接到第一电压的第一端子，连接到第一节点的第二端子和施加数据的栅极。 第二晶体管可以具有连接到第一节点的第一端子和连接到输出节点的第二端子。 噪声消除部分可以连接在第一晶体管的栅极和第二晶体管的栅极之间。 噪声消除部分可以是电容器。 由于第二晶体管的栅极和输出节点之间的耦合电容以及第二晶体管的栅极与第一节点之间的耦合电容，电容器可以基本上消除在第二晶体管的栅极处引入的耦合噪声， 施加到第一晶体管的栅极。

公开(公告)号：US20050212552A1

公开(公告)日：2005-09-29

申请号：US11075470

申请日：2005-03-08

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： G11C7/10 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/018528

摘要： The present invention discloses a semiconductor integrated circuit device and an on-die termination circuit. The circuit includes a level shifter for boosting an on-die termination control signal to a high voltage level; and a first NMOS transistor connected between a power voltage and a pad and terminating the pad to a first termination voltage level in response to the high voltage level. The on-die termination circuit has a reduced input capacitance.

摘要翻译： 本发明公开了一种半导体集成电路器件和片上终端电路。 该电路包括用于将片上终端控制信号升压到高电压电平的电平移位器; 以及连接在电源电压和焊盘之间的第一NMOS晶体管，并且响应于高电压电平将焊盘端接到第一终端电压电平。 片上终端电路具有减小的输入电容。

公开(公告)号：US06847242B2

公开(公告)日：2005-01-25

申请号：US10825204

申请日：2004-04-16

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03M1/68 ,  G11C7/16 ,  G11C7/22 ,  H03L7/081 ,  H03L7/089 ,  H03M1/06 ,  H03M1/08 ,  H03M1/66 ,  H03M1/74 ,  H03M7/00 ,  H03L7/06

CPC分类号： H03M1/0687 ,  G11C7/16 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/089 ,  H03M1/0863 ,  H03M1/664 ,  H03M1/745

摘要： A delay-locked loop (DLL) may include: a variable delay line arrangement operable to receive a reference clock and to output a delayed local clock; a phase comparator device operable to compare said reference clock and said local clock and to provide an up/down indication; and a delay control circuit, responsive to said up/down count-indication, to provide a reduced-noise delay control signal to said variable delay line arrangement, said delay control circuit being operable to count said up/down indication using an escalator code arrangement.

摘要翻译： 延迟锁定环（DLL）可以包括：可变延迟线布置，其可操作以接收参考时钟并输出延迟的本地时钟; 相位比较器装置，可操作以比较所述参考时钟和所述本地时钟并提供上/下指示; 以及延迟控制电路，响应于所述向上/向下计数指示，向所述可变延迟线装置提供降噪噪声延迟控制信号，所述延迟控制电路可操作以使用自动扶梯代码排列来计数所述上/下指示 。

公开(公告)号：US06778114B2

公开(公告)日：2004-08-17

申请号：US10251873

申请日：2002-09-23

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03M166

CPC分类号： H03M1/0687 ,  G11C7/16 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/089 ,  H03M1/0863 ,  H03M1/664 ,  H03M1/745

摘要： A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

摘要翻译： 数模转换器（DAC）可以包括：自动扶梯代码发生器; 和自动扶梯码模拟转换器（ECAC）。 发生器可以（1）代表具有硬币代码部分和现金代码部分的混合代码的基数10，这将在计数方向改变时消除现金代码中的多位变化; 和（2）表示作为硬币代码和现金代码的总和的第一方向的计数。 当计数改变方向时，发电机可以改变硬币代码，而现金代码保持相同，直到超过硬币代码的计数能力，此时可以更改现金代码。 相邻基数10之间的循环被硬币代码吸收，同时保持现金代码相同，这降低了由于这种循环引入到ECAC的输出中的噪声。

公开(公告)号：US07248083B2

公开(公告)日：2007-07-24

申请号：US10815695

申请日：2004-04-02

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H04L25/028

摘要： Systems and methods for decreasing transmission timing variations include precharging a data channel at a level before data is sent over the channel. The driver sets the level in response to the reception of a precharging control signal.

摘要翻译： 用于减少传输定时变化的系统和方法包括在通过信道发送数据之前的级别对数​​据信道进行预充电。 驱动器响应于预充电控制信号的接收而设置电平。