公开(公告)号：US08912831B1

公开(公告)日：2014-12-16

申请号：US13541964

申请日：2012-07-05

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

IPC: H03L7/06 ,  H03L7/187

CPC classification number: H03L7/187 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17784 ,  H04L25/0272 ,  H04L25/0282

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract translation: 信号路由装置包括用于存储一组数据信号的寄存器组。 延迟锁定环产生一组相移位时钟信号。 相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。 连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。 相移位的时钟信号代替更高的时钟频率，以便降低功耗。

公开(公告)号：US06956920B1

公开(公告)日：2005-10-18

申请号：US09531862

申请日：2000-03-21

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

IPC: H03K19/173 ,  H03K19/177 ,  H03L7/06 ,  H04L25/02 ,  H04L25/40

CPC classification number: H03L7/187 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17784 ,  H04L25/0272 ,  H04L25/0282

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract translation: 信号路由装置包括用于存储一组数据信号的寄存器组。 延迟锁定环产生一组相移位时钟信号。 相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。 连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。 相移位的时钟信号代替更高的时钟频率，以便降低功耗。

公开(公告)号：US07593499B1

公开(公告)日：2009-09-22

申请号：US11198097

申请日：2005-08-04

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

IPC: H04L24/40 ,  H04L23/00 ,  H03D3/24

CPC classification number: H03L7/187 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17784 ,  H04L25/0272 ,  H04L25/0282

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract translation: 信号路由装置包括用于存储一组数据信号的寄存器组。 延迟锁定环产生一组相移位时钟信号。 相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。 连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。 相移位的时钟信号代替更高的时钟频率，以便降低功耗。

公开(公告)号：US08233577B1

公开(公告)日：2012-07-31

申请号：US12555237

申请日：2009-09-08

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Robert Bielby

IPC: H04L25/40 ,  H04L23/00 ,  H03D3/24

CPC classification number: H03L7/187 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17784 ,  H04L25/0272 ,  H04L25/0282

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract translation: 信号路由装置包括用于存储一组数据信号的寄存器组。 延迟锁定环产生一组相移位时钟信号。 相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。 连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。 相移位的时钟信号代替更高的时钟频率，以便降低功耗。

公开(公告)号：US06286114B1

公开(公告)日：2001-09-04

申请号：US09186607

申请日：1998-11-06

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

IPC: G06F1125

CPC classification number: G01R31/3177 ,  G01R31/318516 ,  G06F11/25 ,  G06F11/27 ,  G06F11/3636 ,  G06F11/3656 ,  G06F17/5027

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

Abstract translation: 在可编程逻辑器件中嵌入逻辑分析仪可以在触发条件（断点）之前和之后捕获信号。 嵌入在PLD中的逻辑分析仪捕获并存储逻辑信号。 它会卸载这些信号，以便在计算机上查看。 使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，断点，要存储的样本总数，断点发生后要捕获的样本数，以及 系统时钟信号。 EDA工具自动将逻辑分析仪插入PLD的电子设计中，PLD的编译和下载以配置PLD。 使用连接在PLD和计算机之间的接口，EDA工具命令嵌入式逻辑分析仪运行。 信号在环形缓冲RAM存储器中运行时连续存储。 一旦发生断点，除了在断点之前捕获的信号之外，如果需要，还会捕获更多的采样。 EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，以便在计算机上显示。 可以更改断点和样本编号，无需重新编译。 JTAG端口控制逻辑分析仪。 逻辑分析仪的输入和输出被路由到无键JTAG的I / O单元。 或者，用户实现的测试数据寄存器提供了类似JTAG的逻辑元件链，控制和输出信息通过该逻辑元件被移位。 激励单元向逻辑分析仪提供控制信息，并且感测单元从逻辑分析仪检索数据。

公开(公告)号：US06704889B2

公开(公告)日：2004-03-09

申请号：US10212839

申请日：2002-08-06

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

IPC: G06F1125

CPC classification number: G01R31/3177 ,  G01R31/318516 ,  G06F11/25 ,  G06F11/27 ,  G06F11/3636 ,  G06F11/3656 ,  G06F17/5027

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

Abstract translation: 在可编程逻辑器件中嵌入逻辑分析仪可以在触发条件（断点）之前和之后捕获信号。 嵌入在PLD中的逻辑分析仪捕获并存储逻辑信号。 它会卸载这些信号，以便在计算机上查看。 使用在计算机系统上运行的电子设计自动化（EDA）软件工具，工程师指定要监视的PLD的信号，断点，要存储的样本总数，断点发生后要捕获的样本数，以及 系统时钟信号。 EDA工具自动将逻辑分析仪插入PLD的电子设计中，PLD的编译和下载以配置PLD。 使用连接在PLD和计算机之间的接口，EDA工具命令嵌入式逻辑分析仪运行。 信号在环形缓冲RAM存储器中运行时连续存储。 一旦发生断点，除了在断点之前捕获的信号之外，如果需要，还会捕获更多的采样。 EDA工具指示逻辑分析仪从其捕获缓冲区卸载数据，以便在计算机上显示。 可以更改断点和样本编号，无需重新编译。 JTAG端口控制逻辑分析仪。 逻辑分析仪的输入和输出被路由到无键JTAG的I / O单元。 或者，用户实现的测试数据寄存器提供了类似JTAG的逻辑元件链，控制和输出信息通过该逻辑元件被移位。 激励单元向逻辑分析仪提供控制信息，并且感测单元从逻辑分析仪检索数据。

公开(公告)号：US06300790B1

公开(公告)日：2001-10-09

申请号：US09366938

申请日：1999-08-04

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

IPC: H03K19173

Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.

公开(公告)号：US06472903B1

公开(公告)日：2002-10-29

申请号：US09366938

申请日：1999-08-04

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

IPC: H03K19173

CPC classification number: H03K19/17736 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17744 ,  H03K19/17788

Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.

公开(公告)号：US06460148B2

公开(公告)日：2002-10-01

申请号：US09887918

申请日：2001-06-21

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  Alan L. Herrmann

IPC: G06F1125

CPC classification number: G01R31/3177 ,  G01R31/318516 ,  G06F11/25 ,  G06F11/27 ,  G06F11/3636 ,  G06F11/3656 ,  G06F17/5027

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

公开(公告)号：US06377069B1

公开(公告)日：2002-04-23

申请号：US09847800

申请日：2001-05-02

Applicant: Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

Inventor： Kerry Veenstra ,  Krishna Rangasayee ,  John E. Turner

IPC: H03K19173

CPC classification number: H03K19/17736 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17744 ,  H03K19/17788

Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.

Abstract translation: 在可编程逻辑器件中，输入/输出电路被分组成块。 每个块包括能够处理多个逻辑信令方案的输入/输出电路，其可能需要不同的电源电压和参考电压。 每个块也有自己的电源总线。 以这种方式，可以为不同的块提供不同的电源和参考电压，使得不同的块可以用于不同的逻辑信令方案，从而允许在单个设备上同时使用多于一个的这种方案。 只要块中使用的所有方案具有相同的电源要求，并且每个这样的方案需要参考电压 - 相同的参考电压 要求。