公开(公告)号：US11520653B2

公开(公告)日：2022-12-06

申请号：US17071941

申请日：2020-10-15

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Ankur Behl ,  Garima Sharda

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/263

摘要： A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.

公开(公告)号：US20240353479A1

公开(公告)日：2024-10-24

申请号：US18458382

申请日：2023-08-30

申请人： NXP USA, Inc.

发明人： Kumar Abhishek ,  Neha Srivastava ,  Vivek Kumar Yadav ,  Sanjaykumar Hansrajbhai Kakasaniya ,  Vikram Joshi

IPC分类号： G01R31/28 ,  H03K3/037

CPC分类号： G01R31/2884 ,  H03K3/037 ,  H03K19/20

摘要： A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.

公开(公告)号：US11018657B1

公开(公告)日：2021-05-25

申请号：US17247864

申请日：2020-12-28

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Stefan Doll ,  Neha Srivastava

IPC分类号： H03K5/133 ,  H03K5/00

摘要： A clock glitch alerting circuit is configured to detect a glitch in an input clock signal, and activate and provide an alert signal to a security controller when the glitch is detected. The clock glitch alerting circuit is further configured to delay the input clock signal based on multiple selection signals, and provide one of a delayed clock output signal and a filtered clock output signal to the security controller based on the alert signal. The clock glitch alerting circuit is further configured to generate and provide a count value to the security controller that indicates a time duration available by the security controller to execute a security critical operation after receiving the activated alert signal.

公开(公告)号：US11609821B2

公开(公告)日：2023-03-21

申请号：US17039576

申请日：2020-09-30

申请人： NXP USA, Inc.

发明人： Ankur Behl ,  Neha Srivastava

IPC分类号： G06F11/14 ,  G06F11/30 ,  G06F11/07 ,  G06F13/40

摘要： A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.

公开(公告)号：US11422185B2

公开(公告)日：2022-08-23

申请号：US16917663

申请日：2020-06-30

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Garima Sharda

IPC分类号： G01R31/317 ,  G01R31/3177

摘要： A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

公开(公告)号：US20220209759A1

公开(公告)日：2022-06-30

申请号：US17247949

申请日：2020-12-31

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Ateet Mishra ,  Ankur Behl ,  Nancy Mishra ,  Kriti Garg

IPC分类号： H03K5/135 ,  G06F30/3308

摘要： A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.

公开(公告)号：US20220121512A1

公开(公告)日：2022-04-21

申请号：US17071941

申请日：2020-10-15

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Ankur Behl ,  Garima Sharda

IPC分类号： G06F11/07 ,  G06F11/263

摘要： A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.

公开(公告)号：US20220100607A1

公开(公告)日：2022-03-31

申请号：US17039576

申请日：2020-09-30

申请人： NXP USA, Inc.

发明人： Ankur Behl ,  Neha Srivastava

IPC分类号： G06F11/14 ,  G06F13/40

摘要： A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.

公开(公告)号：US20240192745A1

公开(公告)日：2024-06-13

申请号：US18315678

申请日：2023-05-11

申请人： NXP USA, Inc.

发明人： Kumar Abhishek ,  Neha Srivastava ,  Yi Zheng ,  Nishant Kumar

IPC分类号： G06F1/24

CPC分类号： G06F1/24

摘要： Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

公开(公告)号：US11482992B2

公开(公告)日：2022-10-25

申请号：US17247949

申请日：2020-12-31

申请人： NXP USA, Inc.

发明人： Neha Srivastava ,  Ateet Mishra ,  Ankur Behl ,  Nancy Mishra ,  Kriti Garg

IPC分类号： H03K5/135 ,  G06F30/3308 ,  G06F111/04 ,  G06F115/02 ,  H03K5/00

摘要： A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.