公开(公告)号：US20240353479A1

公开(公告)日：2024-10-24

申请号：US18458382

申请日：2023-08-30

申请人： NXP USA, Inc.

发明人： Kumar Abhishek ,  Neha Srivastava ,  Vivek Kumar Yadav ,  Sanjaykumar Hansrajbhai Kakasaniya ,  Vikram Joshi

IPC分类号： G01R31/28 ,  H03K3/037

CPC分类号： G01R31/2884 ,  H03K3/037 ,  H03K19/20

摘要： A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.