公开(公告)号：US11170109B2

公开(公告)日：2021-11-09

申请号：US16386244

申请日：2019-04-16

申请人： NXP USA, INC.

发明人： Rohit Kumar Sinha ,  Arun Jain ,  Himanshu Shekhar Thakur ,  Neha Agarwal

IPC分类号： G06F9/4401 ,  G06F21/57 ,  G06F9/24 ,  G06F12/14

摘要： An SoC device has a boot-code memory that stores boot code and a boot core that accesses the boot-code memory to execute the boot code at startup. The boot core is capable of executing application code after the startup is complete. One or more master cores execute application code. An access control circuit prevents the boot core from accessing the boot-code memory when application code is being executed.

公开(公告)号：US20220197332A1

公开(公告)日：2022-06-23

申请号：US17247651

申请日：2020-12-18

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Garima Sharda ,  Vandana Sapra ,  Amol Agarwal ,  Stefan Doll ,  Andreas Lentz

IPC分类号： G06F1/14

摘要： A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

公开(公告)号：US20220382322A1

公开(公告)日：2022-12-01

申请号：US17814269

申请日：2022-07-22

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Garima Sharda ,  Vandana Sapra ,  Amol Agarwal ,  Stefan Doll ,  Andreas Lentz

IPC分类号： G06F1/14

摘要： A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

公开(公告)号：US20200334361A1

公开(公告)日：2020-10-22

申请号：US16386244

申请日：2019-04-16

申请人： NXP USA, INC.

发明人： Rohit Kumar Sinha ,  Arun Jain ,  Himanshu Shekhar Thakur ,  Neha Agarwal

IPC分类号： G06F21/57 ,  G06F9/4401 ,  G06F12/14 ,  G06F9/24

摘要： An SoC device has a boot-code memory that stores boot code and a boot core that accesses the boot-code memory to execute the boot code at startup. The boot core is capable of executing application code after the startup is complete. One or more master cores execute application code. An access control circuit prevents the boot core from accessing the boot-code memory when application code is being executed.

公开(公告)号：US11609600B2

公开(公告)日：2023-03-21

申请号：US17814269

申请日：2022-07-22

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Garima Sharda ,  Vandana Sapra ,  Amol Agarwal ,  Stefan Doll ,  Andreas Lentz

IPC分类号： G06F1/14 ,  G06F1/12 ,  G06F1/10

摘要： A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

公开(公告)号：US11429142B2

公开(公告)日：2022-08-30

申请号：US17247651

申请日：2020-12-18

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Garima Sharda ,  Vandana Sapra ,  Amol Agarwal ,  Stefan Doll ,  Andreas Lentz

IPC分类号： G06F1/14

摘要： A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

公开(公告)号：US11222707B1

公开(公告)日：2022-01-11

申请号：US17247946

申请日：2020-12-31

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Tomasz Szuprycinski ,  Deepak Mahajan ,  Ruchi Bora

IPC分类号： G11C29/02

摘要： A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.

公开(公告)号：US11018657B1

公开(公告)日：2021-05-25

申请号：US17247864

申请日：2020-12-28

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Stefan Doll ,  Neha Srivastava

IPC分类号： H03K5/133 ,  H03K5/00

摘要： A clock glitch alerting circuit is configured to detect a glitch in an input clock signal, and activate and provide an alert signal to a security controller when the glitch is detected. The clock glitch alerting circuit is further configured to delay the input clock signal based on multiple selection signals, and provide one of a delayed clock output signal and a filtered clock output signal to the security controller based on the alert signal. The clock glitch alerting circuit is further configured to generate and provide a count value to the security controller that indicates a time duration available by the security controller to execute a security critical operation after receiving the activated alert signal.

公开(公告)号：US10911035B1

公开(公告)日：2021-02-02

申请号：US16866428

申请日：2020-05-04

申请人： NXP USA, Inc.

发明人： Rohit Kumar Sinha ,  Amol Agarwal ,  Vandana Sapra

IPC分类号： H03K5/1252 ,  H03K19/003 ,  H03K5/00

摘要： A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.