公开(公告)号：US20240303209A1

公开(公告)日：2024-09-12

申请号：US18665365

申请日：2024-05-15

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C29/02 ,  H03K5/00 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/081 ,  H03L7/10

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10 ,  H03K2005/00019

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

公开(公告)号：US20170075837A1

公开(公告)日：2017-03-16

申请号：US15237473

申请日：2016-08-15

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  H03K5/13 ,  G06F13/42

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation. Several fringe timing points are sampled, whereby several of the plurality of fringe timing points are associated with each of the transition edges of the second stream of data bits input to the data interface circuit. The drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

Abstract translation: 描述了数据接口电路，其中进行用于数据位捕获的校准调整而不干扰正常的系统操作。 定义了用于采样经过训练的最佳采样点以及前导和后采样点的多个DLL捕获和延迟电路。 第一数据比特流被输入到数据接口电路，并且使用第一校准方法，建立用于采样数据位输入的第一最佳采样点。 在正常的系统操作期间，第二数据位流被输入到数据接口电路。 执行与执行第一，第二校准方法不同的第二校准方法，由此：建立至少一个参考数据路径，用于在正常系统操作期间对输入到数据接口的第二数据位流进行采样过渡沿。 多个边缘定时点被采样，其中多个边缘定时点中的几个与输入到数据接口电路的第二数据位流的每个过渡边缘相关联。 将漂移量与漂移校正阈值进行比较，并且第一最佳采样点在时间上偏移漂移量以修改第一最佳采样点。

公开(公告)号：US09425778B2

公开(公告)日：2016-08-23

申请号：US14850792

申请日：2015-09-10

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: H03K5/13 ,  H03K5/14 ,  H03L7/10 ,  G06F13/16 ,  H03L7/08 ,  G11C8/18 ,  G11C29/02 ,  H03L7/081 ,  H03K5/00

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10

Abstract: A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.

Abstract translation: 公开了一种用于数据接口的连续自适应定时校准功能。 对于任务数据路径，通常在上电时执行第一校准方法以建立最佳采样点。 建立不影响正常系统操作的第二校准方法的参考数据路径。 在最佳采样点两侧的边缘定时点检查数据位边沿转换。 假设边缘跃迁的定时变化指示最佳采样点的漂移，当确定漂移量大于校正阈值时，相应地调整任务路径的最佳采样点。 由于始终保持最佳采样点，所以连续校准功能无论确定任何数据位无效。 此外，连续校准无需连续的交替数据位值，例如1-0-1或0-1-0。

公开(公告)号：US08941422B2

公开(公告)日：2015-01-27

申请号：US14205225

申请日：2014-03-11

Applicant: Uniquify, Inc.

Inventor： Venkat Iyer ,  Prashant Joshi ,  Jung Lee

IPC: H03L7/06 ,  H03L7/08

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10

Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.

Abstract translation: 公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。 建立通过闪光灯对数据位进行采样的任务数据通路。 建立类似的参考数据路径用于校准目的。 在初始化时间，两个路径被校准，并且它们之间的增量值被建立。 在任务路径的操作期间，校准路径连续执行校准操作，以确定其最佳延迟是否已经改变超过阈值。 如果是这样，则使用参考路径的新延迟设置，将调整后的任务路径的延迟设置改变为delta值。 还公开了用于对参考路径执行多个并行校准以加速训练过程的电路和方法。

公开(公告)号：US11714769B2

公开(公告)日：2023-08-01

申请号：US17724221

申请日：2022-04-19

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  G06F13/16 ,  H03L7/081 ,  G11C29/02 ,  H03L7/10 ,  H03L7/08 ,  G11C8/18 ,  H03K5/133 ,  H03K5/14 ,  G06F13/42 ,  H03K5/00

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10 ,  H03K2005/00019

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

公开(公告)号：US20220237134A1

公开(公告)日：2022-07-28

申请号：US17724221

申请日：2022-04-19

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  G06F13/16 ,  H03L7/081 ,  G11C29/02 ,  H03L7/10 ,  H03L7/08 ,  G11C8/18 ,  H03K5/133 ,  H03K5/14 ,  G06F13/42

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

公开(公告)号：US08941423B2

公开(公告)日：2015-01-27

申请号：US14205254

申请日：2014-03-11

Applicant: Uniquify, Inc.

Inventor： Venkat Iyer ,  Prashant Joshi ,  Jung Lee

IPC: H03L7/06 ,  H03L7/08

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10

Abstract: Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.

Abstract translation: 公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。 建立通过闪光灯对数据位进行采样的任务数据通路。 建立类似的参考数据路径用于校准目的。 在初始化时间，两个路径被校准，并且它们之间的增量值被建立。 在任务路径的操作期间，校准路径连续执行校准操作，以确定其最佳延迟是否已经改变超过阈值。 如果是这样，则使用参考路径的新延迟设置，将调整后的任务路径的延迟设置改变为delta值。 还公开了用于对参考路径执行多个并行校准以加速训练过程的电路和方法。

公开(公告)号：US12019573B2

公开(公告)日：2024-06-25

申请号：US18209083

申请日：2023-06-13

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: H03K5/14 ,  G06F13/16 ,  G06F13/362 ,  G06F13/42 ,  G11C8/18 ,  G11C29/02 ,  H03K5/133 ,  H03L7/08 ,  H03L7/081 ,  H03L7/10 ,  H03K5/00

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10 ,  H03K2005/00019

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

公开(公告)号：US11334509B2

公开(公告)日：2022-05-17

申请号：US17074403

申请日：2020-10-19

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  H03L7/10 ,  G06F13/16 ,  H03L7/081 ,  G11C29/02 ,  H03L7/08 ,  G11C8/18 ,  H03K5/133 ,  H03K5/14 ,  G06F13/42 ,  H03K5/00

Abstract: A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

公开(公告)号：US20240104038A1

公开(公告)日：2024-03-28

申请号：US18209083

申请日：2023-06-13

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C29/02 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/081 ,  H03L7/10

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10 ,  H03K2005/00019

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.