- 专利标题： Multi-reset and multi-clock synchronizer, and synchronous multi-cycle reset synchronization circuit
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申请号： US17762677申请日： 2020-08-17
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公开(公告)号： US11973504B2公开(公告)日： 2024-04-30
- 发明人: Leon Zlotnik , Lev Zlotnik , Jeremy Anderson
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 代理机构： NICHOLSON DE VOS WEBSTER & ELLIOTT LLP
- 国际申请： PCT/US2020/046704 2020.08.17
- 国际公布： WO2021/080671A 2021.04.29
- 进入国家日期： 2022-03-22
- 主分类号： H03K5/135
- IPC分类号： H03K5/135 ; G06F1/24 ; H03K19/17704 ; H03K19/20
摘要：
An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
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