公开(公告)号：US20250159949A1

公开(公告)日：2025-05-15

申请号：US18507230

申请日：2023-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Ni YU ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Chun-Fu LU ,  Shih-Hao LAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes nanostructures extending in a first direction above a substrate and spaced apart in a second direction perpendicular to the first direction, a gate dielectric layer wrapping around each of the nanostructures, a first p-type work function metal layer between the adjacent nanostructures, a second p-type work function metal layer in contact with opposite sidewalls of the first p-type work function metal layer and opposite sidewalls of the gate dielectric layer, and an n-type work function metal layer covering the second p-type work function metal layer. The second p-type work function metal layer comprises a main layer and a cap layer over the main layer, wherein the cap layer has a material different from a material of the main layer.

公开(公告)号：US20240363732A1

公开(公告)日：2024-10-31

申请号：US18769168

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/7851

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.

公开(公告)号：US20250107152A1

公开(公告)日：2025-03-27

申请号：US18472768

申请日：2023-09-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Shih-Hao LAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

公开(公告)号：US20240322013A1

公开(公告)日：2024-09-26

申请号：US18188964

申请日：2023-03-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Fu LU ,  Chih-Hao Wang ,  Wang-Chun Huang ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391

Abstract: A method for manufacturing a semiconductor structure includes forming first and second channel layers over a substrate, forming first source/drain features over the first and second channel layers, forming a gate dielectric layer wrapping around the first and second channel layers, forming a first work function layer wrapping around the gate dielectric layer, forming a hard mask layer wrapping around the first work function layer, removing portions of the hard mask layer and the first work function layer, removing the hard mask layer and the first work function layer wrapping around the second channel layer, removing the hard mask layer wrapping around the first channel layer, forming a second work function layer wrapping around the first work function layer and the second channel layer, forming a metal material between the second work function layer, and forming second source/drain features under the first and second channel layers.

公开(公告)号：US20240120402A1

公开(公告)日：2024-04-11

申请号：US18513562

申请日：2023-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Chun-Fu LU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66545

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

公开(公告)号：US20220302275A1

公开(公告)日：2022-09-22

申请号：US17207573

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  LUNG-KUN CHU ,  Chung-Wei HSU ,  Chun-Fu LU ,  CHIH-HAO WANG ,  KUAN-LUN CHENG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

公开(公告)号：US20250120123A1

公开(公告)日：2025-04-10

申请号：US18421144

申请日：2024-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Fu LU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chung-Wei HSU ,  Shih-Hao LAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

公开(公告)号：US20240243186A1

公开(公告)日：2024-07-18

申请号：US18155296

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Fu LU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/28575 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.

公开(公告)号：US20240113195A1

公开(公告)日：2024-04-04

申请号：US18172703

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Ni YU ,  Lung-Kun CHU ,  Chun-Fu LU ,  Chung-Wei HSU ,  Mao-Lin HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0642 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66545

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

公开(公告)号：US20230127045A1

公开(公告)日：2023-04-27

申请号：US18068388

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.