公开(公告)号：US20240379670A1

公开(公告)日：2024-11-14

申请号：US18206609

申请日：2023-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Hu ,  Chih-Yi Wang ,  Yao-Jhan Wang ,  Wei-Che Chen ,  Kun-Szu Tseng ,  Yun-Yang He ,  Wen-Liang Huang ,  Lung-En Kuo ,  Po-Tsang Chen ,  Po-Chang Lin ,  Ying-Hsien Chen

IPC: H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

公开(公告)号：US20250015186A1

公开(公告)日：2025-01-09

申请号：US18227299

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chun Lee ,  Chih-Yi Wang ,  Wei-Che Chen ,  Ya-Ting Hu ,  Yao-Jhan Wang ,  Kun-Szu Tseng ,  Feng-Yun Cheng ,  Shyan-Liang Chou

IPC: H01L29/78 ,  H01L25/16

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.

公开(公告)号：US20240363430A1

公开(公告)日：2024-10-31

申请号：US18203654

申请日：2023-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Wei-Che Chen ,  Hung-Chun Lee ,  Yun-Yang He ,  Wei-Hao Chang ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang ,  Ying-Hsien Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

公开(公告)号：US09330920B1

公开(公告)日：2016-05-03

申请号：US14660913

申请日：2015-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Che Chen ,  Chun-Mao Chiou

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a gate structure on the first region, in which the gate structure comprises a first hard mask and a second hard mask thereon; forming a first mask layer on the first region and the second region; removing part of the first mask layer; removing the second hard mask; forming a second mask layer on the first region and the second region; removing part of the second mask layer; and removing the first hard mask.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有限定在其上的第一区域和第二区域的衬底; 在所述第一区域上形成栅极结构，其中所述栅极结构包括第一硬掩模和第二硬掩模; 在所述第一区域和所述第二区域上形成第一掩模层; 去除所述第一掩模层的一部分; 去除第二个硬掩模; 在所述第一区域和所述第二区域上形成第二掩模层; 去除所述第二掩模层的一部分; 并移除第一硬掩模。

公开(公告)号：US20240413017A1

公开(公告)日：2024-12-12

申请号：US18220839

申请日：2023-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Ya-Ting Hu ,  Wei-Che Chen ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.