公开(公告)号：US11783893B2

公开(公告)日：2023-10-10

申请号：US17133459

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Aliasgar S. Madraswala ,  Yihua Zhang

IPC: G11C7/10 ,  G11C11/56 ,  G11C29/42

CPC classification number: G11C11/5628 ,  G11C7/1039 ,  G11C11/5642 ,  G11C29/42

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

公开(公告)号：US20220004495A1

公开(公告)日：2022-01-06

申请号：US17475984

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Chace Clark ,  Francis Corrado ,  Shivashekar Muralishankar ,  Suresh Nagarajan

IPC: G06F12/0802 ,  G06F3/06

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

公开(公告)号：US20170364275A1

公开(公告)日：2017-12-21

申请号：US15186716

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Arun S. Athreya ,  Sanjeev N. Trika

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0634 ,  G06F3/0659 ,  G06F12/0246

Abstract: Technologies for managing end of life behavior of a storage device include an apparatus that includes a memory that includes a plurality of storage cells and a controller to manage read and write operations of the memory. The controller is to determine whether the memory is presently operated in a read-only mode due to a presence of an end of life condition, determine, in response to a determination that the memory is presently operated in the read-only mode and in response to an action of a host, whether to transition the memory to a temporary write mode, and transition, in response to a determination to transition the memory to a temporary write mode, the memory to the temporary write mode. Other embodiments are described and claimed.

公开(公告)号：US11237732B2

公开(公告)日：2022-02-01

申请号：US16532996

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Yihua Zhang

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04

Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

公开(公告)号：US10996860B2

公开(公告)日：2021-05-04

申请号：US16176465

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Shankar Natarajan

IPC: G06F3/06

Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.

公开(公告)号：US20190267080A1

公开(公告)日：2019-08-29

申请号：US16288268

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Sriram Natarajan ,  Suresh Nagarajan ,  Ramkarthik Ganesan ,  Arun S. Athreya ,  Romesh B. Trivedi

IPC: G11C11/56 ,  G11C16/20 ,  G06F12/06 ,  G11C16/16

Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

公开(公告)号：US20240354209A1

公开(公告)日：2024-10-24

申请号：US18762492

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/20 ,  G06F1/30 ,  G06F11/16 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US12099420B2

公开(公告)日：2024-09-24

申请号：US17133834

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/16 ,  G06F11/20 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US12094545B2

公开(公告)日：2024-09-17

申请号：US18235727

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Arun Sitaram Athreya ,  Shankar Natarajan ,  Sriram Natarajan ,  Yihua Zhang ,  Suresh Nagarajan

IPC: G11C11/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

公开(公告)号：US12019558B2

公开(公告)日：2024-06-25

申请号：US17122152

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Scott Crippin ,  Sahar Khalili ,  Shankar Natarajan ,  Romesh Trivedi

IPC: G06F12/10 ,  G06F12/1009 ,  G11C16/04

CPC classification number: G06F12/1009 ,  G06F2212/657 ,  G11C16/0483

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.