MACHINE-LEARNING ERROR-CORRECTING CODE CONTROLLER

    公开(公告)号:US20220116057A1

    公开(公告)日:2022-04-14

    申请号:US17495474

    申请日:2021-10-06

    Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

    LOW-POWER SYSTEMATIC ECC ENCODER WITH BALANCING BITS

    公开(公告)号:US20240372568A1

    公开(公告)日:2024-11-07

    申请号:US18142703

    申请日:2023-05-03

    Abstract: Systems, devices, and methods for encoding information bits for storage, including obtaining information bits and a target constraints vector, placing the information bits in an input vector, setting balance bits included in the input vector to zero, encoding the input vector using a systematic code to obtain a preliminary codeword, applying a constraints matrix to the preliminary codeword to obtain a preliminary constraints vector, applying a transition matrix to a sum of the preliminary constraints vector and the target constraints vector to determine updated balance bits, obtaining an output codeword based on the information bits and the updated balance bits, and storing the output codeword in the storage device.

    SUPER-HPC ERROR CORRECTION CODE
    7.
    发明申请

    公开(公告)号:US20200295783A1

    公开(公告)日:2020-09-17

    申请号:US16352052

    申请日:2019-03-13

    Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.

    SOFT REED-SOLOMON DECODER FOR A NON-VOLATILE MEMORY

    公开(公告)号:US20240137048A1

    公开(公告)日:2024-04-25

    申请号:US18045576

    申请日:2022-10-11

    CPC classification number: H03M13/1575 H03M13/1111 H03M13/1545

    Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

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