Invention Application
- Patent Title: STATE-DEPENDENT FAIL BIT COUNT CRITERIA FOR MEMORY APPARATUS PROGRAM PERFORMANCE GAIN
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Application No.: US18231368Application Date: 2023-08-08
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Publication No.: US20250054556A1Publication Date: 2025-02-13
- Inventor: Jiacen Guo , Xiang Yang , Henry Chin
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C16/08 ; G11C16/10

Abstract:
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.
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