公开(公告)号：US12015026B2

公开(公告)日：2024-06-18

申请号：US17473285

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/22 ,  G11C16/26 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/06 ,  H10B41/40 ,  H10B43/40

CPC classification number: H01L27/0266 ,  G11C16/22 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/3212 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0649 ,  H10B41/40 ,  H10B43/40 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/31116 ,  H01L21/32137

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US10431577B2

公开(公告)日：2019-10-01

申请号：US15892625

申请日：2018-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/115 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/28 ,  H01L21/3213 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/311

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US20190206856A1

公开(公告)日：2019-07-04

申请号：US15892625

申请日：2018-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22

CPC classification number: H01L27/0266 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/22 ,  G11C16/26 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32137 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/0649

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US20160195581A1

公开(公告)日：2016-07-07

申请号：US15069316

申请日：2016-03-14

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

公开(公告)号：US20160155513A1

公开(公告)日：2016-06-02

申请号：US15019397

申请日：2016-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffery A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

公开(公告)号：US12237278B2

公开(公告)日：2025-02-25

申请号：US18142992

申请日：2023-05-03

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

公开(公告)号：US20240395325A1

公开(公告)日：2024-11-28

申请号：US18647354

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  James E. Davis ,  Kenneth W. Marr

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B99/00

Abstract: A semiconductor device including a substrate; a substrate; a memory array disposed on the substrate, the memory array including one or more memory planes, and a plurality of source region contact (SRC) nodes that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate; a plurality of high-voltage (HV) diodes that are disposed in the substrate and that are connected to corresponding SRC nodes, the HV diodes including a first type dopant material; and a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate.

公开(公告)号：US20240071516A1

公开(公告)日：2024-02-29

申请号：US17897448

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth W. Marr ,  James E. Davis ,  Chiara Cerafogli

IPC: G11C16/22 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/16

Abstract: A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.

公开(公告)号：US10665307B2

公开(公告)日：2020-05-26

申请号：US16432059

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G01R31/02 ,  G11C16/10 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G01R31/28 ,  G01R31/30 ,  G11C16/26 ,  G11C29/12 ,  G11C16/00

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.

公开(公告)号：US09761322B2

公开(公告)日：2017-09-12

申请号：US15019397

申请日：2016-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffery A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04 ,  G01R31/02 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G11C29/12

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.