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公开(公告)号：US20240036740A1
公开(公告)日：2024-02-01
申请号：US17983870
申请日：2022-11-09
发明人： Yihang Liu , Xiaochen Zhu , Jie Liu , Sarath Puthenthermadam , Jiahui Yuan , Feng Gao
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0679
摘要： A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.
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公开(公告)号：US11783903B2
公开(公告)日：2023-10-10
申请号：US17511966
申请日：2021-10-27
发明人： Xiang Yang , Xiaochen Zhu
CPC分类号： G11C16/3445 , G11C16/0433 , G11C16/08 , G11C16/102 , G11C16/14 , G11C16/24 , G11C16/28 , G11C16/3404
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.
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公开(公告)号：US20230125748A1
公开(公告)日：2023-04-27
申请号：US17511966
申请日：2021-10-27
发明人： Xiang Yang , Xiaochen Zhu
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.
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公开(公告)号：US12087373B2
公开(公告)日：2024-09-10
申请号：US17873617
申请日：2022-07-26
发明人： Yi Song , Lito De La Rama , Xiaochen Zhu
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16
摘要： An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.
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公开(公告)号：US12046294B2
公开(公告)日：2024-07-23
申请号：US17847553
申请日：2022-06-23
发明人： Yihang Liu , Xiaochen Zhu , Lito De La Rama , Feng Gao
CPC分类号： G11C16/16 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.
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公开(公告)号：US20240233847A1
公开(公告)日：2024-07-11
申请号：US18357274
申请日：2023-07-24
发明人： Yi Song , Jiahui Yuan , Xiaochen Zhu , Lito De La Rama
CPC分类号： G11C29/021 , G11C29/022 , G11C29/52
摘要： A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.
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公开(公告)号：US20240177778A1
公开(公告)日：2024-05-30
申请号：US18357436
申请日：2023-07-24
发明人： Yihang Liu , Xiaochen Zhu , Peng Wang , Jie Liu , Lito De La Rama , Feng Gao , Xiaoyu Yang
CPC分类号： G11C16/12 , G11C16/0433 , G11C16/08 , G11C16/3495
摘要： A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.
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公开(公告)号：US11955184B2
公开(公告)日：2024-04-09
申请号：US17740429
申请日：2022-05-10
发明人： Jiacen Guo , Xiaochen Zhu , Xiang Yang , Lito De La Rama , Yi Song , Jiahui Yuan
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.
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公开(公告)号：US20240047000A1
公开(公告)日：2024-02-08
申请号：US17873617
申请日：2022-07-26
发明人： Yi Song , Lito De La Rama , Xiaochen Zhu
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16
摘要： An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.
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公开(公告)号：US20230420055A1
公开(公告)日：2023-12-28
申请号：US17847553
申请日：2022-06-23
发明人： Yihang Liu , Xiaochen Zhu , Lito De La Rama , Feng Gao
CPC分类号： G11C16/16 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.
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