公开(公告)号：US20230282273A1

公开(公告)日：2023-09-07

申请号：US18169455

申请日：2023-02-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji TANAKA ,  Daiki KITAGATA

IPC: G11C11/417 ,  G11C11/412

CPC classification number: G11C11/417 ,  G11C11/412 ,  G06F7/5443

Abstract: In the semiconductor device according to an embodiment, a memory cell is controlled such that, for the part whose output value can be fixed based on the value stored in the memory cell without performing the information processing, the operation processing is stopped so as to stop the charging and discharging to and from the data line, and for the part whose output value needs to be fixed by performing the information processing, the information processing accompanied by charging and discharging to and from the data line is appropriately performed.

公开(公告)号：US20180240513A1

公开(公告)日：2018-08-23

申请号：US15957263

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20140016391A1

公开(公告)日：2014-01-16

申请号：US14026575

申请日：2013-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。

公开(公告)号：US20130194882A1

公开(公告)日：2013-08-01

申请号：US13750328

申请日：2013-01-25

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

IPC: G11C7/22

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

公开(公告)号：US20220036961A1

公开(公告)日：2022-02-03

申请号：US17382923

申请日：2021-07-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji TANAKA ,  Yuichiro ISHII ,  Makoto YABUUCHI

IPC: G11C29/50 ,  G11C11/419 ,  G11C5/06

Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

公开(公告)号：US20170263307A1

公开(公告)日：2017-09-14

申请号：US15606903

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

公开(公告)号：US20170076783A1

公开(公告)日：2017-03-16

申请号：US15211364

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

Abstract translation: 半导体存储装置包括多个存储模块，其中可以基于第一和第二控制信号来设置和取消多个低功耗模式。 多个存储器模块的至少一部分存储器模块具有将输入的第一控制信号传播到后级存储器模块的传播路径。 第二控制信号并行地输入到多个存储器模块中的每一个。 基于通过传播路径传播的第一控制信号和第二控制信号的组合来执行每个存储器模块的第一低功耗模式的设置和取消。 根据传播的第一控制信号，依次执行每个存储器模块的设置和取消其中关闭电源的区域与第一低功耗模式的区域不同的第二低功耗模式 传播路径。

公开(公告)号：US20160240246A1

公开(公告)日：2016-08-18

申请号：US15134981

申请日：2016-04-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20230317151A1

公开(公告)日：2023-10-05

申请号：US18169463

申请日：2023-02-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daiki KITAGATA ,  Shinji TANAKA

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.

公开(公告)号：US20180366184A1

公开(公告)日：2018-12-20

申请号：US16062571

申请日：2016-11-14

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Shinji TANAKA

IPC: G11C11/419 ,  G11C8/08 ,  G11C7/12

Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.