公开(公告)号：US20190355712A1

公开(公告)日：2019-11-21

申请号：US16528177

申请日：2019-07-31

Applicant: Renesas Electronics Corporation

Inventor： Yuta YOSHIDA ,  Makoto YABUUCHI ,  Yoshisato YOKOYAMA

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/419 ,  H01L27/092 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.

公开(公告)号：US20190259454A1

公开(公告)日：2019-08-22

申请号：US16250448

申请日：2019-01-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI

IPC: G11C15/04

Abstract: A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.

公开(公告)号：US20190198507A1

公开(公告)日：2019-06-27

申请号：US16178227

申请日：2018-11-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Makoto YABUUCHI

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  G11C15/04 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C11/412 ,  G11C15/04 ,  H01L23/528 ,  H01L27/0207

Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.

公开(公告)号：US20190139966A1

公开(公告)日：2019-05-09

申请号：US16239835

申请日：2019-01-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Makoto YABUUCHI ,  Yasumasa TSUKAMOTO ,  Kengo MASUDA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10 ,  H01L27/02 ,  H01L21/265 ,  H01L29/66

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US20180342522A1

公开(公告)日：2018-11-29

申请号：US16014920

申请日：2018-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Makoto YABUUCHI ,  Yasumasa TSUKAMOTO ,  Kengo MASUDA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L21/265

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/1083 ,  H01L29/66659

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US20180340978A1

公开(公告)日：2018-11-29

申请号：US15916016

申请日：2018-03-08

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G01R31/3177 ,  G11C15/04 ,  G06F11/27

Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

公开(公告)号：US20180315471A1

公开(公告)日：2018-11-01

申请号：US16030943

申请日：2018-07-10

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417 ,  G11C5/04 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

公开(公告)号：US20170358344A1

公开(公告)日：2017-12-14

申请号：US15481345

申请日：2017-04-06

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Makoto YABUUCHI ,  Masao MORIMOTO

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418

Abstract: A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.

公开(公告)号：US20170263334A1

公开(公告)日：2017-09-14

申请号：US15606637

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: G11C29/12 ,  G11C11/412 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  H01L27/11 ,  G11C11/419

CPC classification number: G11C29/1201 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/1104 ,  H01L27/1116

Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.

公开(公告)号：US20160133315A1

公开(公告)日：2016-05-12

申请号：US14981195

申请日：2015-12-28

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。