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    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190034260A1

    公开(公告)日：2019-01-31

    申请号：US16152052

    申请日：2018-10-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    SEMICONDUCTOR STORAGE DEVICE
    4.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20180366184A1

    公开(公告)日：2018-12-20

    申请号：US16062571

    申请日：2016-11-14

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Shinji TANAKA

    IPC: G11C11/419 ,  G11C8/08 ,  G11C7/12

    Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190189197A1

    公开(公告)日：2019-06-20

    申请号：US16176299

    申请日：2018-10-31

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Yuichiro ISHII ,  Yohei SAWADA ,  Makoto YABUUCHI

    IPC: G11C11/419 ,  G11C11/412

    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

    SEMICONDUCTOR STORAGE DEVICE
    8.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20150248929A1

    公开(公告)日：2015-09-03

    申请号：US14634743

    申请日：2015-02-28

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII

    IPC: G11C11/419 ,  G11C5/14

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

    Abstract translation: 半导体存储装置包括由驱动晶体管，转移晶体管和负载晶体管组成的SRAM存储单元，连接到与存储单元连接的位线的I / O电路，以及操作模式控制电路， 在恢复待机模式和正常操作模式之间的I / O电路的模式，其中I / O电路包括将数据写入位线的写入驱动器，从位线读取数据的读出放大器，插入的第一开关 在位线和写入驱动器之间，插入在位线和读出放大器之间的第二开关，预充电位线的预充电电路，以及根据信号控制第一和第二开关和预充电电路的控制电路 从操作模式控制电路。

    SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS 有权
    具有读写存取存取操作的时序控制的半导体器件

    公开(公告)号：US20130194882A1

    公开(公告)日：2013-08-01

    申请号：US13750328

    申请日：2013-01-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

    IPC: G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

    Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

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