公开(公告)号：US20190034260A1

公开(公告)日：2019-01-31

申请号：US16152052

申请日：2018-10-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/073

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

公开(公告)号：US20170352399A1

公开(公告)日：2017-12-07

申请号：US15613882

申请日：2017-06-05

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato YOKOYAMA ,  Yoshikazu SAITO ,  Shunya NAGATA ,  Toshiaki SANO ,  Takeshi HASHIZUME

IPC: G11C11/405 ,  G11C8/16 ,  G11C7/06 ,  G11C11/406 ,  H03K19/177 ,  G11C11/408

CPC classification number: G11C11/405 ,  G11C7/062 ,  G11C8/16 ,  G11C11/40603 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/32 ,  G11C2029/1202 ,  G11C2207/104 ,  H03K19/1776

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

公开(公告)号：US20210241808A1

公开(公告)日：2021-08-05

申请号：US17158301

申请日：2021-01-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunya NAGATA ,  Yoshikazu SAITO ,  Takeshi HASHIZUME

IPC: G11C8/10 ,  G11C8/08 ,  G11C7/18 ,  G11C7/06

Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

公开(公告)号：US20130194882A1

公开(公告)日：2013-08-01

申请号：US13750328

申请日：2013-01-25

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

IPC: G11C7/22

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

公开(公告)号：US20180047457A1

公开(公告)日：2018-02-15

申请号：US15782662

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Yuichiro ISHII ,  Masaki TSUKUDE ,  Yoshikazu SAITO

IPC: G11C29/02 ,  G11C11/419 ,  G11C29/50 ,  G11C29/18 ,  G11C11/418 ,  G11C29/12 ,  G11C29/04 ,  G11C29/28

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.

公开(公告)号：US20180018211A1

公开(公告)日：2018-01-18

申请号：US15710803

申请日：2017-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/073

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

公开(公告)号：US20150023091A1

公开(公告)日：2015-01-22

申请号：US14504994

申请日：2014-10-02

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

公开(公告)号：US20170092378A1

公开(公告)日：2017-03-30

申请号：US15234910

申请日：2016-08-11

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Yuichiro ISHll ,  Masaki TSUKUDE ,  Yoshikazu SAITO

IPC: G11C29/12 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

公开(公告)号：US20160358667A1

公开(公告)日：2016-12-08

申请号：US15240863

申请日：2016-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

IPC: G11C29/12 ,  G11C11/417

CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏;测试地址存储单元，被配置为存储测试地址; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

公开(公告)号：US20160092293A1

公开(公告)日：2016-03-31

申请号：US14868238

申请日：2015-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/073

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

Abstract translation: 本发明提供一种可以通过具有低面积开销的简单方法执行地址解码器的故障检测的半导体存储器件。 半导体存储器件包括：具有以矩阵排列的多个第一存储单元的第一存储器阵列; 与每个存储单元行对应地提供的多个字线; 地址解码器，用于根据输入的地址信息从字线中选择字线; 在列方向上与第一存储器阵列相邻设置的第二存储器阵列，具有多个第二存储单元，能够读取在先前存储的字线的选择中使用的地址信息，根据扩展的字线的选择 到第二存储器阵列; 以及比较电路，用于将输入地址信息与从第二存储器阵列读取的地址信息进行比较。